Levi I.
30
Coauthors
9
Documentos
Volumen de publicaciones por año
Cargando gráfico
| Año de publicación | Num. Publicaciones |
|---|---|
| 2014 | 1 |
| 2015 | 1 |
| 2016 | 2 |
| 2017 | 1 |
| 2018 | 1 |
| 2019 | 2 |
| 2023 | 1 |
Publicaciones por áreas de conocimiento
Cargando gráfico
| Área de conocimiento | Num. Publicaciones |
|---|---|
| Ingeniería electrónica | 14 |
| Simulación por computadora | 1 |
| Arquitectura de computadoras | 1 |
Publicaciones por áreas temáticas
Cargando gráfico
| Área temática | Num. Publicaciones |
|---|---|
| Física aplicada | 7 |
| Ciencias de la computación | 3 |
| Medicina y salud | 1 |
| Economía | 1 |
Principales fuentes de datos
| Origen | Num. Publicaciones |
|---|---|
| Scopus | 9 |
| Google Scholar | 0 |
| RRAAE | 0 |
Cargando gráfico
Coautores destacados por número de publicaciones
| Coautor | Num. Publicaciones |
|---|---|
| Fish A. | 9 |
| Marco Lanuzza | 9 |
| Ramiro Taco | 9 |
| Shavit N. | 1 |
| Stanger I. | 1 |
| Yavits L. | 1 |
Cargando gráfico
Top Keywords
Cargando gráfico
Publicaciones del autor
An 88-fJ/40-MHz [0.4 V]-0.61-pJ/1-GHz [0.9 V] dual-mode logic 8 × 8 bit multiplier accumulator with a self-adjustment mechanism in 28-nm FD-SOI
ArticleAbstract: The unique ability of dual-mode logic (DML) to self-adapt to computational needs by providing high sPalabras claves:Dual-mode logic (DML), high-speed, Low-power, self-adaptive multiply-accumulate (MAC)Autores:Fish A., Levi I., Marco Lanuzza, Ramiro TacoFuentes:scopusExploring back biasing opportunities in 28nm UTBB FD-SOI technology for subthreshold digital design
Conference ObjectAbstract: Ultra-Thin Body and Box Fully Depleted silicon on insulator (UTBB FD-SOI) has been identified as attPalabras claves:28nm UTBB FD-SOI, Back biasing, Single Well, Subthreshold digital designAutores:Fish A., Levi I., Marco Lanuzza, Ramiro TacoFuentes:scopusExtended exploration of low granularity back biasing control in 28nm UTBB FD-SOI technology
Conference ObjectAbstract: Recently, we proposed a low-granularity back-bias control technique [1] optimized for the ultra-thinPalabras claves:28nm UTBB FD-SOI, Dynamic body biasing, low voltage designAutores:Fish A., Levi I., Marco Lanuzza, Ramiro TacoFuentes:scopusEnergy-delay tradeoffs of low-voltage dual mode logic in 28nm FD-SOI
Conference ObjectAbstract: In this paper, the Dual Mode Logic (DML) technique is evaluated on a low-voltage 16-bit Carry Skip APalabras claves:carry skip adder, dual mode logic (DML), Low-voltageAutores:Fish A., Levi I., Marco Lanuzza, Ramiro TacoFuentes:scopusEvaluation of Dual Mode Logic in 28nm FD-SOI technology
Conference ObjectAbstract: For the first time, the Dual Mode Logic (DML) technique is evaluated in 28 nm UTBB FD-SOI technologyPalabras claves:dual mode logic (DML), Low PowerAutores:Fish A., Levi I., Marco Lanuzza, Ramiro TacoFuentes:scopus