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Proceedings - IEEE International Symposium on Circuits and Systems(2)
2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015(1)
2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017(1)
IEEE Journal of Solid-State Circuits(1)
Solid-State Electronics(1)
Origen
scopus(6)
An 88-fJ/40-MHz [0.4 V]-0.61-pJ/1-GHz [0.9 V] dual-mode logic 8 × 8 bit multiplier accumulator with a self-adjustment mechanism in 28-nm FD-SOI
ArticleAbstract: The unique ability of dual-mode logic (DML) to self-adapt to computational needs by providing high sPalabras claves:Dual-mode logic (DML), high-speed, Low-power, self-adaptive multiply-accumulate (MAC)Autores:Fish A., Levi I., Marco Lanuzza, Ramiro TacoFuentes:scopusEnergy-delay tradeoffs of low-voltage dual mode logic in 28nm FD-SOI
Conference ObjectAbstract: In this paper, the Dual Mode Logic (DML) technique is evaluated on a low-voltage 16-bit Carry Skip APalabras claves:carry skip adder, dual mode logic (DML), Low-voltageAutores:Fish A., Levi I., Marco Lanuzza, Ramiro TacoFuentes:scopusEvaluation of Dual Mode Logic in 28nm FD-SOI technology
Conference ObjectAbstract: For the first time, the Dual Mode Logic (DML) technique is evaluated in 28 nm UTBB FD-SOI technologyPalabras claves:dual mode logic (DML), Low PowerAutores:Fish A., Levi I., Marco Lanuzza, Ramiro TacoFuentes:scopusLow voltage logic circuits exploiting gate level dynamic body biasing in 28 nm UTBB FD-SOI
ArticleAbstract: In this paper, the recently proposed gate level body bias (GLBB) technique is evaluated for low voltPalabras claves:Dynamic body biasing, Low-voltage logic design, UTBB FD-SOIAutores:Fish A., Levi I., Marco Lanuzza, Ramiro TacoFuentes:scopusLow voltage ripple carry adder with low-granularity dynamic forward back-biasing in 28 nm UTBB FD-SOI
Conference ObjectAbstract: In this paper, a low voltage ripple-carry adder (RCA), designed for the ultra-thin body and box (UTBPalabras claves:FD-SOI, gate-level body biasing, Single WellAutores:Fish A., Levi I., Marco Lanuzza, Ramiro TacoFuentes:scopusLive demo: An 88FJ / 40 MHz [0.4V] - 0.61PJ / 1GHz [0.9V] dual mode logic 8x8-bit multiplier accumulator with a self-adjustment mechanism in 28 nm FD-SOI
Conference ObjectAbstract: The unique ability of dual mode logic (DML) to self-adapt to computational needs by providing high sPalabras claves:Autores:Fish A., Levi I., Marco Lanuzza, Ramiro TacoFuentes:scopus