Mostrando 7 resultados de: 7
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Publisher
Proceedings - IEEE International Symposium on Circuits and Systems(2)
2014 IEEE 28th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2014(1)
2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015(1)
2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017(1)
IEEE Solid-State Circuits Letters(1)
Área de conocimiento
Ingeniería electrónica(4)
Arquitectura de computadoras(1)
Simulación por computadora(1)
Origen
scopus(7)
Exploring back biasing opportunities in 28nm UTBB FD-SOI technology for subthreshold digital design
Conference ObjectAbstract: Ultra-Thin Body and Box Fully Depleted silicon on insulator (UTBB FD-SOI) has been identified as attPalabras claves:28nm UTBB FD-SOI, Back biasing, Single Well, Subthreshold digital designAutores:Fish A., Levi I., Marco Lanuzza, Ramiro TacoFuentes:scopusExtended exploration of low granularity back biasing control in 28nm UTBB FD-SOI technology
Conference ObjectAbstract: Recently, we proposed a low-granularity back-bias control technique [1] optimized for the ultra-thinPalabras claves:28nm UTBB FD-SOI, Dynamic body biasing, low voltage designAutores:Fish A., Levi I., Marco Lanuzza, Ramiro TacoFuentes:scopusFlexDML: High Utilization Configurable Multimode Arithmetic Units Featuring Dual Mode Logic
ArticleAbstract: Dual mode logic (DML) enables flexible energy-delay (ED) optimization. By setting the design elementPalabras claves:Arithmetic, CMOS, configurable computing, DML, dual mode logic (DML), dynamic, mixed-mode, Pipeline, staticAutores:Fish A., Levi I., Marco Lanuzza, Ramiro Taco, Shavit N., Stanger I., Yavits L.Fuentes:scopusEnergy-delay tradeoffs of low-voltage dual mode logic in 28nm FD-SOI
Conference ObjectAbstract: In this paper, the Dual Mode Logic (DML) technique is evaluated on a low-voltage 16-bit Carry Skip APalabras claves:carry skip adder, dual mode logic (DML), Low-voltageAutores:Fish A., Levi I., Marco Lanuzza, Ramiro TacoFuentes:scopusEvaluation of Dual Mode Logic in 28nm FD-SOI technology
Conference ObjectAbstract: For the first time, the Dual Mode Logic (DML) technique is evaluated in 28 nm UTBB FD-SOI technologyPalabras claves:dual mode logic (DML), Low PowerAutores:Fish A., Levi I., Marco Lanuzza, Ramiro TacoFuentes:scopusLow voltage logic circuits exploiting gate level dynamic body biasing in 28 nm UTBB FD-SOI
ArticleAbstract: In this paper, the recently proposed gate level body bias (GLBB) technique is evaluated for low voltPalabras claves:Dynamic body biasing, Low-voltage logic design, UTBB FD-SOIAutores:Fish A., Levi I., Marco Lanuzza, Ramiro TacoFuentes:scopusLow voltage ripple carry adder with low-granularity dynamic forward back-biasing in 28 nm UTBB FD-SOI
Conference ObjectAbstract: In this paper, a low voltage ripple-carry adder (RCA), designed for the ultra-thin body and box (UTBPalabras claves:FD-SOI, gate-level body biasing, Single WellAutores:Fish A., Levi I., Marco Lanuzza, Ramiro TacoFuentes:scopus