An 88-fJ/40-MHz [0.4 V]-0.61-pJ/1-GHz [0.9 V] dual-mode logic 8 × 8 bit multiplier accumulator with a self-adjustment mechanism in 28-nm FD-SOI

Article

Abstract: The unique ability of dual-mode logic (DML) to self-adapt to computational needs by providing high s

Palabras claves:

Dual-mode logic (DML), high-speed, Low-power, self-adaptive multiply-accumulate (MAC)

Autores:

Fish A., Levi I., Marco Lanuzza, Ramiro Taco

Fuentes:

scopus