Albano D.
13
Coauthors
5
Documentos
Volumen de publicaciones por año
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| Año de publicación | Num. Publicaciones |
|---|---|
| 2014 | 1 |
| 2015 | 2 |
| 2017 | 2 |
Publicaciones por áreas de conocimiento
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| Área de conocimiento | Num. Publicaciones |
|---|---|
| Ingeniería electrónica | 9 |
Publicaciones por áreas temáticas
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| Área temática | Num. Publicaciones |
|---|---|
| Física aplicada | 3 |
| Ciencias de la computación | 2 |
Principales fuentes de datos
| Origen | Num. Publicaciones |
|---|---|
| Scopus | 5 |
| Google Scholar | 0 |
| RRAAE | 0 |
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Coautores destacados por número de publicaciones
| Coautor | Num. Publicaciones |
|---|---|
| Marco Lanuzza | 5 |
| Crupi F. | 3 |
| Ramiro Taco | 3 |
| Rose R.D. | 2 |
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Publicaciones del autor
Dynamic gate-level body biasing for subthreshold digital design
Conference ObjectAbstract: Dynamic gate-level body biasing has been recently proposed as an alternative design methodology forPalabras claves:Autores:Albano D., Marco Lanuzza, Ramiro TacoFuentes:scopusUltra-low-voltage self-body biasing scheme and its application to basic arithmetic circuits
ArticleAbstract: The gate level body biasing (GLBB) is assessed in the context of ultra-low-voltage logic designs. ToPalabras claves:Autores:Albano D., Marco Lanuzza, Ramiro TacoFuentes:scopusA physical unclonable function based on a 2-transistor subthreshold voltage divider
ArticleAbstract: In this paper, a compact circuit solution for silicon-based static physical unclonable functions (PUPalabras claves:analog design, CMOS design, Hardware security, physical unclonable functions (PUFs), subthreshold operation, variabilityAutores:Albano D., Crupi F., Marco Lanuzza, Rose R.D.Fuentes:scopusDesign of a sub-1-V nanopower CMOS current reference
Conference ObjectAbstract: In this paper, we propose a sub-1-V nanopower current reference based on dual-threshold voltage currPalabras claves:CMOS analog design, Current reference, low-power design, low-voltage design, subthreshold operationAutores:Albano D., Crupi F., Marco Lanuzza, Rose R.D.Fuentes:scopusGate-level body biasing for subthreshold logic circuits: Analytical modeling and design guidelines
ArticleAbstract: Gate-level body biasing provides an attractive solution to increase speed and robustness against proPalabras claves:digital circuits, forward body biasing, subthreshold design, Ultra-low voltageAutores:Albano D., Crupi F., Marco Lanuzza, Ramiro TacoFuentes:scopus