Mostrando 5 resultados de: 5
Filtros aplicados
Publisher
International Journal of Circuit Theory and Applications(2)
2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings(1)
2017 European Conference on Circuit Theory and Design, ECCTD 2017(1)
VLSI Design(1)
Área de conocimiento
Ingeniería electrónica(5)
A physical unclonable function based on a 2-transistor subthreshold voltage divider
ArticleAbstract: In this paper, a compact circuit solution for silicon-based static physical unclonable functions (PUPalabras claves:analog design, CMOS design, Hardware security, physical unclonable functions (PUFs), subthreshold operation, variabilityAutores:Albano D., Crupi F., Marco Lanuzza, Rose R.D.Fuentes:scopusDesign of a sub-1-V nanopower CMOS current reference
Conference ObjectAbstract: In this paper, we propose a sub-1-V nanopower current reference based on dual-threshold voltage currPalabras claves:CMOS analog design, Current reference, low-power design, low-voltage design, subthreshold operationAutores:Albano D., Crupi F., Marco Lanuzza, Rose R.D.Fuentes:scopusGate-level body biasing for subthreshold logic circuits: Analytical modeling and design guidelines
ArticleAbstract: Gate-level body biasing provides an attractive solution to increase speed and robustness against proPalabras claves:digital circuits, forward body biasing, subthreshold design, Ultra-low voltageAutores:Albano D., Crupi F., Marco Lanuzza, Ramiro TacoFuentes:scopusDynamic gate-level body biasing for subthreshold digital design
Conference ObjectAbstract: Dynamic gate-level body biasing has been recently proposed as an alternative design methodology forPalabras claves:Autores:Albano D., Marco Lanuzza, Ramiro TacoFuentes:scopusUltra-low-voltage self-body biasing scheme and its application to basic arithmetic circuits
ArticleAbstract: The gate level body biasing (GLBB) is assessed in the context of ultra-low-voltage logic designs. ToPalabras claves:Autores:Albano D., Marco Lanuzza, Ramiro TacoFuentes:scopus