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Gate-level body biasing for subthreshold logic circuits: Analytical modeling and design guidelines
ArticleAbstract: Gate-level body biasing provides an attractive solution to increase speed and robustness against proPalabras claves:digital circuits, forward body biasing, subthreshold design, Ultra-low voltageAutores:Albano D., Crupi F., Marco Lanuzza, Ramiro TacoFuentes:scopusUltra-low-voltage self-body biasing scheme and its application to basic arithmetic circuits
ArticleAbstract: The gate level body biasing (GLBB) is assessed in the context of ultra-low-voltage logic designs. ToPalabras claves:Autores:Albano D., Marco Lanuzza, Ramiro TacoFuentes:scopus