Efficient Configuration for a Scalable Spiking Neural Network Platform by means of a Synchronous Address Event Representation bus

Conference Object

Abstract: Hardware architectures for Spiking Neural Networks (SNNs) emulation exhibit accelerated processing t

Palabras claves:

AER (Address Event Representation), Configurability, Fpga, multi-chip platform, PSoC, SNN emulation

Autores:

Janio Jadán-Guerrero, Madrenas J., Mireya Zapata-Rodríguez

Fuentes:

google

scopus