High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator

Conference Object

Abstract: This paper presents an energy-efficient single-clock-cycle binary Dual-Mode Logic (DML)-based compar

Palabras claves:

arithmetic circuits, binary comparator, CMOS, Dual-mode logic

Autores:

Luis Miguel Procel Moya, Marco Lanuzza, Ramiro Taco, Ricardo Escobar, Trojman L.

Fuentes:

scopus