Mostrando 4 resultados de: 4
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Conference Object(4)
Publisher
2020 IEEE ANDESCON, ANDESCON 2020(2)
2019 IEEE 4th Ecuador Technical Chapters Meeting, ETCM 2019(1)
ETCM 2021 - 5th Ecuador Technical Chapters Meeting(1)
Área temáticas
Métodos informáticos especiales(1)
Organizaciones generales en las Islas Británicas; en Inglaterra(1)
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Ciencias de la computación(2)
Ingeniería electrónica(2)
Simulación por computadora(2)
Visión por computadora(1)
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scopus(4)
720p-HD Gray-scale and Color Images Shape Recognition System Implementation on an FPGA Platform with a 1080pFull-HD HDMI Interface using a Hu Moments Algorithm
Conference ObjectAbstract: The present work implements and adapts a fast shape recognition algorithm on the Xilinx VC707 VIRTEXPalabras claves:ADV7511, Fpga, Full-HD, Gray Scale, HDL, HDMI, IIC, RGB, Shape recognitionAutores:André Borja, Daniel Cárdenas, Felipe Toscano, Luis Miguel Prócel Moya, Ramiro Taco, Trojman L.Fuentes:scopusEffects of the technology scaling down to 28nm on Ultra-Low Voltage and Power OTA performance using TCAD simulations
Conference ObjectAbstract: In this paper, the effect on the performances of the technology scaling down to 28nm (bulk and planaPalabras claves:28nm, 90nm, Feed Forward rejection, OTA, PDK, Pseudo Differential Pair, TCAD simulation, Ultra-low power, Ultra-low voltageAutores:André Borja, Juan Orozco, Luis Miguel Prócel Moya, Mateo Bonilla, Mateo Valencia, Ramiro Taco, Trojman L.Fuentes:scopusImplementation and Comparison of a Fast Shape Recognition Algorithm using Different FPGA Platforms
Conference ObjectAbstract: In the present work, we implement and compare a fast shape recognition algorithm in two FPGA platforPalabras claves:computer vison, Fpga, HDL, Shape recognitionAutores:André Borja, Daniel Cárdenas, Germán Arévalo Bermeo, Luis Miguel Prócel Moya, Trojman L., Varengues G.Fuentes:scopusImplementation of 32nm MD5 Crypto-Processor using Different Topographical Synthesis Techniques and Comparison with 500nm Node
Conference ObjectAbstract: This work focuses on several synthetizations developed in both 32nm and 500nm technologies to evaluaPalabras claves:32nm Technology, Integrated circuit, MD5, Synopsys, Synthesis Guide, technology scaling, Topographical SynthesisAutores:André Borja, Juan José Jiménez, Luis Miguel Prócel Moya, Ramiro Taco, Silly L., Trojman L.Fuentes:scopus