Mostrando 5 resultados de: 5
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Publisher
2019 IEEE 4th Ecuador Technical Chapters Meeting, ETCM 2019(2)
2021 IEEE 12th Latin American Symposium on Circuits and Systems, LASCAS 2021(1)
2022 IEEE 13th Latin American Symposium on Circuits and Systems, LASCAS 2022(1)
IEEE Transactions on Circuits and Systems II: Express Briefs(1)
Área temáticas
Ciencias de la computación(4)
Física aplicada(1)
Programación informática, programas, datos, seguridad(1)
DMTJ-Based Non-Volatile Ternary Content Addressable Memory for Energy-Efficient High-Performance Systems
Conference ObjectAbstract: This paper explores performance of non-volatile ternary content addressable memories (NV-TCAMs), expPalabras claves:Double-barrier magnetic tunnel junction, energy-efficiency, Ternary content-addressable memoriesAutores:Kevin Vicuña, Luis Miguel Prócel Moya, Ramiro Taco, Trojman L.Fuentes:googlescopusHigh-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator
Conference ObjectAbstract: This paper presents an energy-efficient single-clock-cycle binary Dual-Mode Logic (DML)-based comparPalabras claves:arithmetic circuits, binary comparator, CMOS, Dual-mode logicAutores:Luis Miguel Prócel Moya, Marco Lanuzza, Ramiro Taco, Ricardo Escobar, Trojman L.Fuentes:scopusXNOR-Bitcount Operation Exploiting Computing-In-Memory With STT-MRAMs
ArticleAbstract: This brief presents an energy-efficient and high-performance XNOR-bitcount architecture exploiting tPalabras claves:bit-quad, BNN, cnn, Computing-in-memory, DMTJ, MAC, spin-transfer torque, STT-MRAM, XNOR-bitcountAutores:Ariana Musello, Esteban Garzón, Luis Miguel Prócel Moya, Marco Lanuzza, Ramiro TacoFuentes:scopusPower and Area Reduction of MD5 based on Cryptoprocessor Using novel approach of Internal Counters on the Finite State Machine
Conference ObjectAbstract: This work presents the design of a very simple microprocessor dedicated to cryptographic operationsPalabras claves:Area Reduction, Integrated circuit, MD5, Power Optimization, Synopsis, System Verilog, Top-Down DesignAutores:Juan José Jiménez, Luis Miguel Prócel Moya, Trojman L.Fuentes:scopusTFET and FinFET Hybrid Technologies for SRAM Cell: Performance Improvement over a Large VDD-Range
Conference ObjectAbstract: This work proposes and compares Static Random-Access Memory (SRAM) cells using hybrid technology forPalabras claves:CMOS, DELAY, FinFET, hybrid, Power consumption, SRAM, Static Noise Margin, TFET, Write Noise MarginAutores:Adriana Arevalo, Liautard R., Luis Miguel Prócel Moya, Trojman L.Fuentes:googlescopus