Mostrando 7 resultados de: 7
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2019 IEEE 4th Ecuador Technical Chapters Meeting, ETCM 2019(2)
2020 IEEE ANDESCON, ANDESCON 2020(1)
2022 IEEE 13th Latin American Symposium on Circuits and Systems, LASCAS 2022(1)
Electronics (Switzerland)(1)
IEEE Transactions on Circuits and Systems II: Express Briefs(1)
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Ciencias de la computación(6)
Física aplicada(2)
Lingüística(1)
Métodos informáticos especiales(1)
Organizaciones generales en las Islas Británicas; en Inglaterra(1)
720p-HD Gray-scale and Color Images Shape Recognition System Implementation on an FPGA Platform with a 1080pFull-HD HDMI Interface using a Hu Moments Algorithm
Conference ObjectAbstract: The present work implements and adapts a fast shape recognition algorithm on the Xilinx VC707 VIRTEXPalabras claves:ADV7511, Fpga, Full-HD, Gray Scale, HDL, HDMI, IIC, RGB, Shape recognitionAutores:André Borja, Daniel Cárdenas, Felipe Toscano, Luis Miguel Prócel Moya, Ramiro Taco, Trojman L.Fuentes:scopusDMTJ-Based Non-Volatile Ternary Content Addressable Memory for Energy-Efficient High-Performance Systems
Conference ObjectAbstract: This paper explores performance of non-volatile ternary content addressable memories (NV-TCAMs), expPalabras claves:Double-barrier magnetic tunnel junction, energy-efficiency, Ternary content-addressable memoriesAutores:Kevin Vicuña, Luis Miguel Prócel Moya, Ramiro Taco, Trojman L.Fuentes:googlescopusEnergy efficient self-adaptive dual mode logic address decoder
ArticleAbstract: This paper presents a 1024-bit self-adaptive memory address decoder based on Dual Mode Logic (DML) dPalabras claves:Address decoder, Controller, Dual mode logic, Self-adaptiveAutores:Ariana Musello, Cristhopher Mosquera, Esteban Garzón, Kevin Vicuña, Luis Miguel Prócel Moya, Mateo Rendón, Ramiro Taco, Sara Benedictis, Trojman L.Fuentes:googlescopusImplementation and Comparison of a Fast Shape Recognition Algorithm using Different FPGA Platforms
Conference ObjectAbstract: In the present work, we implement and compare a fast shape recognition algorithm in two FPGA platforPalabras claves:computer vison, Fpga, HDL, Shape recognitionAutores:André Borja, Daniel Cárdenas, Germán Arévalo Bermeo, Luis Miguel Prócel Moya, Trojman L., Varengues G.Fuentes:scopusXNOR-Bitcount Operation Exploiting Computing-In-Memory With STT-MRAMs
ArticleAbstract: This brief presents an energy-efficient and high-performance XNOR-bitcount architecture exploiting tPalabras claves:bit-quad, BNN, cnn, Computing-in-memory, DMTJ, MAC, spin-transfer torque, STT-MRAM, XNOR-bitcountAutores:Ariana Musello, Esteban Garzón, Luis Miguel Prócel Moya, Marco Lanuzza, Ramiro TacoFuentes:scopusRemote control of VNA and parameter analyzer for RFCV measurements using Python
Conference ObjectAbstract: This paper presents the development of capacitance measurement with RF signal (RFCV) for MOSFET. SucPalabras claves:IEEE 488.2, MOSFET, Network Analyzer, PYTHON, RFCV, SCPI, SMU, VNAAutores:Esteban Garzón, Fernando Sanchez, Luis Miguel Prócel Moya, Trojman L.Fuentes:scopusPower and Area Reduction of MD5 based on Cryptoprocessor Using novel approach of Internal Counters on the Finite State Machine
Conference ObjectAbstract: This work presents the design of a very simple microprocessor dedicated to cryptographic operationsPalabras claves:Area Reduction, Integrated circuit, MD5, Power Optimization, Synopsis, System Verilog, Top-Down DesignAutores:Juan José Jiménez, Luis Miguel Prócel Moya, Trojman L.Fuentes:scopus