Mostrando 3 resultados de: 3
Assessment of 10 nm Tunnel-FETs and FinFETs transistors for ultra-low voltage and high-speed digital circuits
Conference ObjectAbstract: The trade-offs of the Tunnel-FETs (TFETs) in terms of delay, energy per cycle, and noise margin arePalabras claves:digital circuits, Energy-delay trade-off, FinFET, Tunnel-FET (TFET), Ultra-low voltageAutores:Christian Cao, Kevin Landázuri, Luis Miguel Prócel Moya, Mateo Rendón, Ramiro Taco, Trojman L.Fuentes:scopusA 180 nm Low-Cost Operational Amplifier for IoT Applications
Conference ObjectAbstract: This paper presents the design and post-layout simulation of a two-stage operational amplifier (opamPalabras claves:0.18 μ m, cadence virtuoso, High-performance, internet of things (IoT), Low-cost, miller compensation, operational amplifier, post-layout simulation, stabilityAutores:Ariana Musello, Cristhopher Mosquera, Kevin Vicuña, Luis Miguel Prócel Moya, Marco Lanuzza, Mateo Rendón, Ramiro Taco, Trojman L.Fuentes:scopusImplementation of 32nm MD5 Crypto-Processor using Different Topographical Synthesis Techniques and Comparison with 500nm Node
Conference ObjectAbstract: This work focuses on several synthetizations developed in both 32nm and 500nm technologies to evaluaPalabras claves:32nm Technology, Integrated circuit, MD5, Synopsys, Synthesis Guide, technology scaling, Topographical SynthesisAutores:André Borja, Juan José Jiménez, Luis Miguel Prócel Moya, Ramiro Taco, Silly L., Trojman L.Fuentes:scopus