Mostrando 5 resultados de: 5
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2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018(1)
2021 IEEE 12th Latin American Symposium on Circuits and Systems, LASCAS 2021(1)
2022 IEEE 13th Latin American Symposium on Circuits and Systems, LASCAS 2022(1)
IEEE Solid-State Circuits Letters(1)
IEEE Transactions on Circuits and Systems II: Express Briefs(1)
DMTJ-Based Non-Volatile Ternary Content Addressable Memory for Energy-Efficient High-Performance Systems
Conference ObjectAbstract: This paper explores performance of non-volatile ternary content addressable memories (NV-TCAMs), expPalabras claves:Double-barrier magnetic tunnel junction, energy-efficiency, Ternary content-addressable memoriesAutores:Kevin Vicuña, Luis Miguel Prócel Moya, Ramiro Taco, Trojman L.Fuentes:googlescopusFlexDML: High Utilization Configurable Multimode Arithmetic Units Featuring Dual Mode Logic
ArticleAbstract: Dual mode logic (DML) enables flexible energy-delay (ED) optimization. By setting the design elementPalabras claves:Arithmetic, CMOS, configurable computing, DML, dual mode logic (DML), dynamic, mixed-mode, Pipeline, staticAutores:Fish A., Levi I., Marco Lanuzza, Ramiro Taco, Shavit N., Stanger I., Yavits L.Fuentes:scopusHigh-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator
Conference ObjectAbstract: This paper presents an energy-efficient single-clock-cycle binary Dual-Mode Logic (DML)-based comparPalabras claves:arithmetic circuits, binary comparator, CMOS, Dual-mode logicAutores:Luis Miguel Prócel Moya, Marco Lanuzza, Ramiro Taco, Ricardo Escobar, Trojman L.Fuentes:scopusXNOR-Bitcount Operation Exploiting Computing-In-Memory With STT-MRAMs
ArticleAbstract: This brief presents an energy-efficient and high-performance XNOR-bitcount architecture exploiting tPalabras claves:bit-quad, BNN, cnn, Computing-in-memory, DMTJ, MAC, spin-transfer torque, STT-MRAM, XNOR-bitcountAutores:Ariana Musello, Esteban Garzón, Luis Miguel Prócel Moya, Marco Lanuzza, Ramiro TacoFuentes:scopusProcess variation-aware datapath employing dual mode logic
Conference ObjectAbstract: Dual Mode Logic (DML), which was recently introduced by our group, offers the possibility to operatePalabras claves:dual mode logic (DML), Dynamic logic, Process variation, Static cmos, Ultra-low voltageAutores:Fish A., Ramiro Taco, Shavit N., Stanger I.Fuentes:scopus