Mostrando 10 resultados de: 30
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Proceedings - IEEE International Symposium on Circuits and Systems(6)
Electronics (Switzerland)(4)
2022 IEEE 13th Latin American Symposium on Circuits and Systems, LASCAS 2022(3)
ETCM 2021 - 5th Ecuador Technical Chapters Meeting(3)
2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings(2)
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Física aplicada(22)
Ciencias de la computación(12)
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Assessment of 10 nm Tunnel-FETs and FinFETs transistors for ultra-low voltage and high-speed digital circuits
Conference ObjectAbstract: The trade-offs of the Tunnel-FETs (TFETs) in terms of delay, energy per cycle, and noise margin arePalabras claves:digital circuits, Energy-delay trade-off, FinFET, Tunnel-FET (TFET), Ultra-low voltageAutores:Christian Cao, Kevin Landázuri, Luis Miguel Prócel Moya, Mateo Rendón, Ramiro Taco, Trojman L.Fuentes:scopusA 0.8-V, 1.54-pJ/940-MHz Dual-Mode Logic-Based 16×16-b Booth Multiplier in 16-nm FinFET
ArticleAbstract: The dual-mode logic (DML) defines runtime adapted digital architectures that switch to either improvPalabras claves:Adaptive design, digital signal processing (DSP), Dual-mode logic (DML)Autores:Fish A., Marco Lanuzza, Ramiro Taco, Shavit N., Stanger I.Fuentes:scopusA 180 nm Low-Cost Operational Amplifier for IoT Applications
Conference ObjectAbstract: This paper presents the design and post-layout simulation of a two-stage operational amplifier (opamPalabras claves:0.18 μ m, cadence virtuoso, High-performance, internet of things (IoT), Low-cost, miller compensation, operational amplifier, post-layout simulation, stabilityAutores:Ariana Musello, Cristhopher Mosquera, Kevin Vicuña, Luis Miguel Prócel Moya, Marco Lanuzza, Mateo Rendón, Ramiro Taco, Trojman L.Fuentes:scopusA Method for Mitigation of Droop Timing Errors Including a 500 MHz Droop Detector and Dual Mode Logic
ArticleAbstract: A technique to mitigate timing errors induced by power supply droops is featured. We propose an invePalabras claves:Capacitors, Clocks, Detectors, Inverters, Logic gates, Resonant frequency, timingAutores:Fish A., Ramiro Taco, Shavit N., Shifman Y., Shor J., Stanger I.Fuentes:scopusDMTJ-Based Non-Volatile Ternary Content Addressable Memory for Energy-Efficient High-Performance Systems
Conference ObjectAbstract: This paper explores performance of non-volatile ternary content addressable memories (NV-TCAMs), expPalabras claves:Double-barrier magnetic tunnel junction, energy-efficiency, Ternary content-addressable memoriesAutores:Kevin Vicuña, Luis Miguel Prócel Moya, Ramiro Taco, Trojman L.Fuentes:googlescopusAn 88-fJ/40-MHz [0.4 V]-0.61-pJ/1-GHz [0.9 V] dual-mode logic 8 × 8 bit multiplier accumulator with a self-adjustment mechanism in 28-nm FD-SOI
ArticleAbstract: The unique ability of dual-mode logic (DML) to self-adapt to computational needs by providing high sPalabras claves:Dual-mode logic (DML), high-speed, Low-power, self-adaptive multiply-accumulate (MAC)Autores:Fish A., Levi I., Marco Lanuzza, Ramiro TacoFuentes:scopusFrom 32 nm to TFET Technology: New Perspectives for Ultra-Scaled RF-DC Multiplier Circuits
ArticleAbstract: In this present work, different Cross-Coupled Differential Drive (CCDD) CMOS bridge rectifiers are dPalabras claves:32 nm, CCDD, Full wave rectifier, Multiplier, PCE, TFET, VCEAutores:Eduardo Ortiz-Holguin, Luis Miguel Prócel Moya, Marco Villegas, Ramiro Taco, Trojman L.Fuentes:googlescopusGate-level body biasing for subthreshold logic circuits: Analytical modeling and design guidelines
ArticleAbstract: Gate-level body biasing provides an attractive solution to increase speed and robustness against proPalabras claves:digital circuits, forward body biasing, subthreshold design, Ultra-low voltageAutores:Albano D., Crupi F., Marco Lanuzza, Ramiro TacoFuentes:scopusExploiting single-well design for energy-efficient ultra-wide voltage range Dual Mode Logic -based digital circuits in 28nm FD-SOI technology
Conference ObjectAbstract: In this paper we evaluate the implementation options of energy-efficient dual mode logic (DML) circuPalabras claves:Adaptive energy-efficient digital design, Dual mode logic, FD-SOIAutores:Fish A., Marco Lanuzza, Ramiro Taco, Shavit N., Stanger I., Yavits L.Fuentes:scopusEnergy efficient self-adaptive dual mode logic address decoder
ArticleAbstract: This paper presents a 1024-bit self-adaptive memory address decoder based on Dual Mode Logic (DML) dPalabras claves:Address decoder, Controller, Dual mode logic, Self-adaptiveAutores:Ariana Musello, Cristhopher Mosquera, Esteban Garzón, Kevin Vicuña, Luis Miguel Prócel Moya, Mateo Rendón, Ramiro Taco, Sara Benedictis, Trojman L.Fuentes:googlescopus