Mostrando 10 resultados de: 26
Filtros aplicados
Publisher
Proceedings - IEEE International Symposium on Circuits and Systems(6)
Electronics (Switzerland)(4)
2021 IEEE 12th Latin American Symposium on Circuits and Systems, LASCAS 2021(2)
2022 IEEE 13th Latin American Symposium on Circuits and Systems, LASCAS 2022(2)
ETCM 2021 - 5th Ecuador Technical Chapters Meeting(2)
Área temáticas
Ciencias de la computación(8)
Ingeniería y operaciones afines(2)
Economía(1)
Instrumentos de precisión y otros dispositivos(1)
Medicina y salud(1)
Assessment of 10 nm Tunnel-FETs and FinFETs transistors for ultra-low voltage and high-speed digital circuits
Conference ObjectAbstract: The trade-offs of the Tunnel-FETs (TFETs) in terms of delay, energy per cycle, and noise margin arePalabras claves:digital circuits, Energy-delay trade-off, FinFET, Tunnel-FET (TFET), Ultra-low voltageAutores:Christian Cao, Kevin Landázuri, Luis Miguel Prócel Moya, Mateo Rendón, Ramiro Taco, Trojman L.Fuentes:scopusA 180 nm Low-Cost Operational Amplifier for IoT Applications
Conference ObjectAbstract: This paper presents the design and post-layout simulation of a two-stage operational amplifier (opamPalabras claves:0.18 μ m, cadence virtuoso, High-performance, internet of things (IoT), Low-cost, miller compensation, operational amplifier, post-layout simulation, stabilityAutores:Ariana Musello, Cristhopher Mosquera, Kevin Vicuña, Luis Miguel Prócel Moya, Marco Lanuzza, Mateo Rendón, Ramiro Taco, Trojman L.Fuentes:scopusA Method for Mitigation of Droop Timing Errors Including a 500 MHz Droop Detector and Dual Mode Logic
ArticleAbstract: A technique to mitigate timing errors induced by power supply droops is featured. We propose an invePalabras claves:Capacitors, Clocks, Detectors, Inverters, Logic gates, Resonant frequency, timingAutores:Fish A., Ramiro Taco, Shavit N., Shifman Y., Shor J., Stanger I.Fuentes:scopusFrom 32 nm to TFET Technology: New Perspectives for Ultra-Scaled RF-DC Multiplier Circuits
ArticleAbstract: In this present work, different Cross-Coupled Differential Drive (CCDD) CMOS bridge rectifiers are dPalabras claves:32 nm, CCDD, Full wave rectifier, Multiplier, PCE, TFET, VCEAutores:Eduardo Ortiz-Holguin, Luis Miguel Prócel Moya, Marco Villegas, Ramiro Taco, Trojman L.Fuentes:googlescopusGate-level body biasing for subthreshold logic circuits: Analytical modeling and design guidelines
ArticleAbstract: Gate-level body biasing provides an attractive solution to increase speed and robustness against proPalabras claves:digital circuits, forward body biasing, subthreshold design, Ultra-low voltageAutores:Albano D., Crupi F., Marco Lanuzza, Ramiro TacoFuentes:scopusExploiting single-well design for energy-efficient ultra-wide voltage range Dual Mode Logic -based digital circuits in 28nm FD-SOI technology
Conference ObjectAbstract: In this paper we evaluate the implementation options of energy-efficient dual mode logic (DML) circuPalabras claves:Adaptive energy-efficient digital design, Dual mode logic, FD-SOIAutores:Fish A., Marco Lanuzza, Ramiro Taco, Shavit N., Stanger I., Yavits L.Fuentes:scopusExploring back biasing opportunities in 28nm UTBB FD-SOI technology for subthreshold digital design
Conference ObjectAbstract: Ultra-Thin Body and Box Fully Depleted silicon on insulator (UTBB FD-SOI) has been identified as attPalabras claves:28nm UTBB FD-SOI, Back biasing, Single Well, Subthreshold digital designAutores:Fish A., Levi I., Marco Lanuzza, Ramiro TacoFuentes:scopusExtended exploration of low granularity back biasing control in 28nm UTBB FD-SOI technology
Conference ObjectAbstract: Recently, we proposed a low-granularity back-bias control technique [1] optimized for the ultra-thinPalabras claves:28nm UTBB FD-SOI, Dynamic body biasing, low voltage designAutores:Fish A., Levi I., Marco Lanuzza, Ramiro TacoFuentes:scopusFlexDML: High Utilization Configurable Multimode Arithmetic Units Featuring Dual Mode Logic
ArticleAbstract: Dual mode logic (DML) enables flexible energy-delay (ED) optimization. By setting the design elementPalabras claves:Arithmetic, CMOS, configurable computing, DML, dual mode logic (DML), dynamic, mixed-mode, Pipeline, staticAutores:Fish A., Levi I., Marco Lanuzza, Ramiro Taco, Shavit N., Stanger I., Yavits L.Fuentes:scopusEnergy efficient self-adaptive dual mode logic address decoder
ArticleAbstract: This paper presents a 1024-bit self-adaptive memory address decoder based on Dual Mode Logic (DML) dPalabras claves:Address decoder, Controller, Dual mode logic, Self-adaptiveAutores:Ariana Musello, Cristhopher Mosquera, Esteban Garzón, Kevin Vicuña, Luis Miguel Prócel Moya, Mateo Rendón, Ramiro Taco, Sara Benedictis, Trojman L.Fuentes:googlescopus