Mostrando 3 resultados de: 3
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Publisher
2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015(1)
International Journal of Circuit Theory and Applications(1)
VLSI Design(1)
Área de conocimiento
Ingeniería electrónica(3)
Origen
scopus(3)
Gate-level body biasing for subthreshold logic circuits: Analytical modeling and design guidelines
ArticleAbstract: Gate-level body biasing provides an attractive solution to increase speed and robustness against proPalabras claves:digital circuits, forward body biasing, subthreshold design, Ultra-low voltageAutores:Albano D., Crupi F., Marco Lanuzza, Ramiro TacoFuentes:scopusLow voltage ripple carry adder with low-granularity dynamic forward back-biasing in 28 nm UTBB FD-SOI
Conference ObjectAbstract: In this paper, a low voltage ripple-carry adder (RCA), designed for the ultra-thin body and box (UTBPalabras claves:FD-SOI, gate-level body biasing, Single WellAutores:Fish A., Levi I., Marco Lanuzza, Ramiro TacoFuentes:scopusUltra-low-voltage self-body biasing scheme and its application to basic arithmetic circuits
ArticleAbstract: The gate level body biasing (GLBB) is assessed in the context of ultra-low-voltage logic designs. ToPalabras claves:Autores:Albano D., Marco Lanuzza, Ramiro TacoFuentes:scopus