A Variation-Aware Timing Modeling Approach for Write Operation in Hybrid CMOS/STT-MTJ Circuits

Article

Abstract: In this paper, a variation-aware simulation framework for hybrid circuits comprising MOS transistors

Palabras claves:

device-circuit simulation, process variability, Spintronic circuits, stochastic switching, STT-MRAM

Autores:

Alioto M., Carpentieri M., Crupi F., Finocchio G., Marco Lanuzza, Rose R.D., Siracusano G., Tomasello R.

Fuentes:

scopus