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AER-SRT: Scalable spike distribution by means of synchronous serial ring topology address event representation
ArticleAbstract: Given the massive number of interconnects in Spiking Neural Networks (SNNs), distributing spikes effPalabras claves:AER (Address Event Representation), Aurora protocol, Multi-chip communication, SNN emulation, Synchronous serial ring, Time slot emulationAutores:Dorta T., Madrenas J., Mireya Zapata-Rodríguez, Sánchez G.Fuentes:googlescopusSNAVA—A real-time multi-FPGA multi-model spiking neural network simulation architecture
ArticleAbstract: Spiking Neural Networks (SNN) for Versatile Applications (SNAVA) simulation platform is a scalable aPalabras claves:Digital neural simulation, Fpga, Neuromorphic systems, SNNsAutores:Cambria S., Dorta T., Krishnamourthy K., Madrenas J., Marti A., Mireya Zapata-Rodríguez, Pirrone V., Sánchez G., Sripad A.Fuentes:googlescopus