Mostrando 4 resultados de: 4
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Publisher
Proceedings - IEEE International Symposium on Circuits and Systems(2)
IEEE Access(1)
IEEE Journal on Emerging and Selected Topics in Circuits and Systems(1)
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scopus(4)
AM<sup>4</sup>: MRAM Crossbar Based CAM/TCAM/ACAM/AP for In-Memory Computing
ArticleAbstract: In-memory computing seeks to minimize data movement and alleviate the memory wall by computing in-siPalabras claves:associative memories, associative processor, CAM, Double-barrier MTJ, emerging memories, MRAM, MTJ, Non-von Neumann computer architecture, TCAMAutores:Esteban Garzón, Marco Lanuzza, Teman A., Yavits L.Fuentes:scopusA Low-Energy DMTJ-Based Ternary Content- Addressable Memory With Reliable Sub-Nanosecond Search Operation
ArticleAbstract: In this paper, we propose an energy-efficient, reliable, hybrid, 10-transistor/2-Double-Barrier-MagnPalabras claves:Double-barrier MTJ, energy-efficiency, Low-power, non-volatile TCAM (NV-TCAM)Autores:Carpentieri M., Esteban Garzón, Finocchio G., Marco Lanuzza, Teman A., Yavits L.Fuentes:scopusExploiting single-well design for energy-efficient ultra-wide voltage range Dual Mode Logic -based digital circuits in 28nm FD-SOI technology
Conference ObjectAbstract: In this paper we evaluate the implementation options of energy-efficient dual mode logic (DML) circuPalabras claves:Adaptive energy-efficient digital design, Dual mode logic, FD-SOIAutores:Fish A., Marco Lanuzza, Ramiro Taco, Shavit N., Stanger I., Yavits L.Fuentes:scopusDual mode logic address decoder
Conference ObjectAbstract: Address decoders are integral components of random access memories. In higher-performance computing,Palabras claves:dual mode logic (DML), Memory address decoderAutores:Fish A., Ramiro Taco, Shavit N., Stanger I., Yavits L.Fuentes:scopus