A Method for Mitigation of Droop Timing Errors Including a 500 MHz Droop Detector and Dual Mode Logic

Article

Abstract: A technique to mitigate timing errors induced by power supply droops is featured. We propose an inve

Palabras claves:

Capacitors, Clocks, Detectors, Inverters, Logic gates, Resonant frequency, timing

Autores:

Fish A., Ramiro Taco, Shavit N., Shifman Y., Shor J., Stanger I.

Fuentes:

scopus