Design and evaluation of high-speed energy-aware carry skip adders

Abstract:

In this paper, the impact of different dynamic logic design styles is evaluated considering as benchmark a fast carryskip adder. Four different adder designs were implemented in standard domino, footless domino, data driven dynamic, and dynamic hybrid (standard domino + data driven dynamic) logic design styles, by exploiting the STMicroelectronics 45nm 1V CMOS technology. When applied to a 32-bit carry-skip adder, the data driven dynamic approach assures an energy-delay product 29%, 33% and 39% lower than the standard domino, footless domino, and dynamic hybrid implementations, respectively. © 2009 IEEE.

Año de publicación:

2010

Keywords:

Fuente:

scopus