Energy-efficient single-clock-cycle binary comparator

Abstract:

A new fast low-power single-clock-cycle binary comparator is presented. High speed is assured by using parallel-prefix architecture, whereas low power is guaranteed by reducing the switching activities of the internal nodes. When implemented with the ST 90 nm 1 V CMOS technology, the proposed circuit exhibits a 4.5 GHz maximum running frequency and 0.77 μW/ MHz energy dissipation. © 2010 John Wiley & Sons, Ltd.

Año de publicación:

2012

Keywords:

• arithmetic circuits
• CMOS
• Low-power
• binary comparator

Fuente:

scopus