An AER handshake-less modular infrastructure PCB with x8 2.5 Gbps LVDS serial links
Abstract:
Nowadays spike-based brain processing emulation is taking off. Several EU and others worldwide projects are demonstrating this, like SpiNNaker, BrainScaleS, FACETS, or NeuroGrid. The larger the brain process emulation on silicon is, the higher the communication performance of the hosting platforms has to be. Many times the bottleneck of these system implementations is not on the performance inside a chip or a board, but in the communication between boards. This paper describes a novel modular Address-Event-Representation (AER) FPGA-based (Spartan6) infrastructure PCB (the AER-Node board) with 2.5Gbps LVDS high speed serial links over SATA cables that offers a peak performance of 32-bit 62.5Meps (Mega events per second) on board-to-board communications. The board allows back compatibility with parallel AER devices supporting up to x2 28-bit parallel data with asynchronous handshake …
Año de publicación:
2014
Keywords:
Fuente:

Tipo de documento:
Other
Estado:
Acceso abierto
Áreas de conocimiento:
- Ingeniería electrónica
- Ingeniería electrónica
- Ingeniería electrónica
Áreas temáticas de Dewey:
- Física aplicada

Objetivos de Desarrollo Sostenible:
- ODS 9: Industria, innovación e infraestructura
- ODS 3: Salud y bienestar
- ODS 4: Educación de calidad
