Fixed point and power consumption analysis of a coherent receiver for optical access networks implemented in FPGA

Abstract:

We demonstrate an FPGA implementation of the key DSP blocks required for a 10Gb/s coherent receiver incorporating tunable lasers and evaluate trade-offs between bit resolution, power consumption and performance. We find that a 3dB reduction in power consumption is possible for a 1.8dB sensitivity penalty.

Año de publicación:

2013

Keywords:

Fuente:

scopus