Hybrid clock recovery for a gigabit POF transceiver implemented on FPGA

Abstract:

In this paper, we present a clock recovery system implemented on field programmable gate array and integrated to the Gigabit Ethernet media converter for PMMA SI-POF developed within the framework of the POF-PLUS EU Project. We demonstrate timing synchronizing using only one sample per symbol from a highly distorted and attenuated 2-PAM signal without requiring any sort of preequalization. This is achieved by means of a hybrid analog-digital PLL with a timing error detector based on a modified version of the Müller and Mueller algorithm, a loop filter, and a VCXO. © 1983-2012 IEEE.

Año de publicación:

2013

Keywords:

• Clock recovery (CR)
• phase-locked loop (PLL)
• DSP
• Optical Communications
• Polymer Optical Fiber
• Field programmable gate array (FPGA)
• timing error detector (TED)
• Gigabit Ethernet

Fuente:

scopus