Impact of process variations on pulsed flip-flops: Yield improving circuit-level techniques and comparative analysis

Abstract:

Process variations cause unpbkp_redictability in speed and power characteristics of nanometer CMOS circuits impacting the timing and energy yields. In this paper, transistor reordering and dual-Vth techniques are evaluated regarding their efficiency in mitigating the impact of process variations on a set of pulsed flip-flops. It is shown that the conjunct use of the above mentioned techniques can improve delay, energy and EDP yields more than 1.98X, 1.62X and 1.99X times, respectively. The yield optimized flip-flop circuits are also comparatively analyzed to identify the best topologies. © 2011 Springer-Verlag Berlin Heidelberg.

Año de publicación:

2011

Keywords:

Fuente:

scopus