Regresar

Pareto efficient design for reconfigurable streaming applications on CPU/FPGAs

Abstract:

We present a Pareto efficient design method for multi-dimensional optimization of run-time reconfigurable streaming applications on CPU/FPGA platforms, which automatically allocates applications with optimized buffer requirement and software/hardware implementation cost. At the same time, application performance is guaranteed with sustainable throughput during run-time reconfigurations. As the main contribution, we formulate the constraint based application allocation, scheduling, and reconfiguration analysis, and propose a design Pareto-point calculation flow. A public domain solver - Gecode is used in solutions finding. The capability of our method has been exemplified by two cases studies on applications from media and communication domains. © 2010 EDAA.

Año de publicación:

2010

Keywords:

    Fuente:

    scopusscopus

    Tipo de documento:

    Conference Object

    Estado:

    Acceso restringido

    Áreas de conocimiento:

    • Simulación por computadora

    Áreas temáticas:

    • Ciencias de la computación

    Contribuidores:

    Ingo SanderIngo Sander
    Jantsch A.Jantsch A.
    Zhu J.Zhu J.