A Programmable Convolution Chip Prototype for Real-Time Image Filtering

Abstract:

A new chip that performs real-time image convolutions with programmable kernels of arbitrary shape is presented. This is a first prototype of reduced size (16x16 pixels) to validate system level techniques. It has been fabricated in AMS-0.35µm, 2-poly, 3-metal technology. Chip inputs and outputs are coded using Address Event Representation (AER). This is an emergent neuromorphic interchip communication protocol that allows for real-time virtual massive connectivity between huge number of pixels located on different chips. Pixels generate ‘events’ according to their activity levels. More active pixels generate more events per unit time and access the interchip communication channel more frequently, whereas pixels with low activity consume less communication bandwidth. This allows to communicate more relevant information in a very short time. Specific PCI boards have been developed to feed images into the chip and to read images out of it.

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