Power and Area Reduction of MD5 based on Cryptoprocessor Using novel approach of Internal Counters on the Finite State Machine

Abstract:

This work presents the design of a very simple microprocessor dedicated to cryptographic operations implementing Message Digest Algorithm 5 (MD5). We tested two control types based on the Moore Finite State Machine: with and without registers as counters. The design was performed with Synopsys TCAD using an open source 500nm technology iPDK. The design using FSM with registers as internal counter results a reduction of 13% on the Silicon area and the simulation demonstrates that we could reach a reduction of 22% of power consumption explained by an 8% decrease of cells required for encryption operations.

Año de publicación:

2019

Keywords:

• Top-Down Design
• System Verilog
• Integrated circuit
• Area Reduction
• MD5
• Synopsis
• Power Optimization

Fuente:

scopus