Regresar

Speech recognition systems and its automatic synthesis in hardware

Abstract:

In this paper a methodology to perform optimizations in the hardware implementation of a speech recognizer is presented; this methodology explores the design space from a very high level representation of the algorithm. We expose how to accelerate the process of speech recognition by exploiting the inherently concurrent decoding stage. Finally, we show the cost in terms of hardware resources required to synthesize the speech recognition algorithms. © 2010 IEEE.

Año de publicación:

2010

Keywords:

    Fuente:

    scopusscopus

    Tipo de documento:

    Conference Object

    Estado:

    Acceso restringido

    Áreas de conocimiento:

      Áreas temáticas:

      • Ciencias de la computación

      Contribuidores:

      Rivera Calle FredyRivera Calle Fredy
      Aedo J.E.Aedo J.E.
      Buitrago J.Buitrago J.