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Towards cognitive reconfigurable hardware: Self-Aware learning in RTR fault-Tolerant SoCs

Abstract:

Traditional embedded systems are evolving into power-And-performance-domain self-Aware intelligent systems in order to overcome complexity and uncertainty. Without human control, they need to keep operative states in applications such as drone-based delivery or robotic space landing. Nowadays, the partial and run-Time reconfiguration (RTR) of FPGA-based Systems-on-chip (SoC) can enable dynamic hardware acceleration or self-healing structures, but this conversely increases system-memory traffic. This paper introduces the basis of cognitive reconfigurable hardware and presents the design of an FPGA-based RTR SoC that becomes conscious of its monitored hardware and learns to make decisions that maintain a desired system performance, particularly when triggering hardware acceleration and dynamic fault-Tolerant (FT) schemes on RTR cores. Self-Awareness is achieved by evaluating monitored metrics in critical AXI-cores, supported by hardware performance counters. We suggest a reinforcement-learning algorithm that helps the system to search out when and which reconfigurable FT-scheme can be triggered. Executing random sequences of an embedded benchmark suite simulates unpbkp_redictability and bus traffic. The evaluation shows the effectiveness and implications of our approach.