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Towards uml-rt behavioural consistency

Abstract:

Having an objective of achieving a formal characterisation of Sequence Diagrams (UML-SD) as a means for Embedded Real-Time software systems C ERTS ) development and validation, this paper introduces a CSP-Tbased timed trace semantics for most concepts of SD. A trace is sequence of events, which gives the necessary expressiveness to capture the standard interpretation of UML SD. Timed SD (TSD) depict work flow, message passing and gives a general view of how system's components cooperate over time to achieve a result. Such sequence, often called an scenario, also represents a part of the system behaviour and a possible execution of a state machine. State machines and SD are used as complementary models for describing system behaviour.