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Using synchronizers for refining synchronous communication onto hardware/software architectures

Abstract:

We have presented a formal set of synchronization components called synchronizers for refining synchronous communication onto HW/SW codesign architectures. Such an architecture imposes asynchronous communication between HW-HW, SW-SW and HW-SW components. The synchronizers enable local synchronization, thus satisfy the synchronization requirement of a typical IP core. In this paper, we present their implementations in HW, SW and HW/SW, as well as their application. To validate our concepts, we conduct a case study on a Nios FPGA that comprises a processor, memory and custom logic. The final HW/SW implementation achieves equivalent performance to pure HW implementation. Our prototyping experience suggests that the synchronizers can be standardized as library modules and effectively separate the design of computation from that of communication. © 2007 IEEE.