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Viterbi decoders generation for FPGA platforms

Abstract:

In this paper, we describe a relation that allows to generate Viterbi decoders for FPGA platforms. These decoders are created from the vectors that describe the adders of a convolutional encoder with code rate 1/2. This relation has been used to implement a script in Matlab, which generates decoders in VHDL language for an FPGA platform from a basic set of entities used to create ACS cells. © 2013 IEEE.