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Viterbi decoders generation for FPGA platforms

Abstract:

In this paper, we describe a relation that allows to generate Viterbi decoders for FPGA platforms. These decoders are created from the vectors that describe the adders of a convolutional encoder with code rate 1/2. This relation has been used to implement a script in Matlab, which generates decoders in VHDL language for an FPGA platform from a basic set of entities used to create ACS cells. © 2013 IEEE.

Año de publicación:

2013

Keywords:

    Fuente:

    scopusscopus

    Tipo de documento:

    Conference Object

    Estado:

    Acceso restringido

    Áreas de conocimiento:

    • Ciencias de la computación

    Áreas temáticas:

    • Física aplicada

    Contribuidores:

    Juan Iván Nieto-HipólitoJuan Iván Nieto-Hipólito
    Reyes S.V.Reyes S.V.
    Sánchez-López J.D.D.Sánchez-López J.D.D.
    Ramos A.E.P.Ramos A.E.P.
    Briseno M.V.Briseno M.V.
    Espinosa L.A.L.Espinosa L.A.L.