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International Journal of Circuit Theory and Applications(4)
IEEE Transactions on Circuits and Systems II: Express Briefs(1)
ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems(1)
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)(1)
Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010(1)
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Física aplicada(6)
Ciencias de la computación(4)
Ingeniería y operaciones afines(1)
Instrumentos de precisión y otros dispositivos(1)
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scopus(10)
An efficient and low-cost design methodology to improve SRAM-Based FPGA robustness in space and avionics applications
Conference ObjectAbstract: This paper presents an efficient approach to protect an FPGA design against Single Event Upsets (SEUPalabras claves:Avionics, Fpga, Reconfigurable System, Single Event Upsets, spaceAutores:Corsonello P., Frustaci F., Marco Lanuzza, Perri S., Zicari P.Fuentes:scopusAnalyzing noise robustness of wide fan-in dynamic logic gates under process variations
ArticleAbstract: Wide fan-in dynamic logic gates are difficult to design due to the large number of leaky evaluationPalabras claves:Dynamic logic, process variations, wide fan-inAutores:Corsonello P., Frustaci F., Marco Lanuzza, Perri S.Fuentes:scopusA new low-power high-speed single-clock-cycle binary comparator
Conference ObjectAbstract: This paper presents a new ultra-low power high-speed single-clock-cycle binary comparator. It is basPalabras claves:Autores:Corsonello P., Frustaci F., Marco Lanuzza, Perri S.Fuentes:scopusDesign of high-speed low-power parallel-prefix adder trees in nanometer technologies
ArticleAbstract: This paper presents a novel approach to design high-speed low-power parallel-prefix adder trees. SubPalabras claves:Brent-Kung adder tree, High-speed addition, Parallel-Prefix addersAutores:Corsonello P., Marco Lanuzza, Perri S.Fuentes:scopusGate-level body biasing technique for high-speed sub-threshold CMOS logic gates
ArticleAbstract: An efficient technique for designing high-performance logic circuits operating in sub-threshold regiPalabras claves:body biasing, Logic gates, sub-threshold CMOS, ultra low-powerAutores:Corsonello P., Marco Lanuzza, Perri S.Fuentes:scopusEnergy-efficient single-clock-cycle binary comparator
ArticleAbstract: A new fast low-power single-clock-cycle binary comparator is presented. High speed is assured by usiPalabras claves:arithmetic circuits, binary comparator, CMOS, Low-powerAutores:Corsonello P., Frustaci F., Marco Lanuzza, Perri S.Fuentes:scopusNew performance/power/area efficient, reliable full adder design
Conference ObjectAbstract: Arithmetic circuits have always played one of the most important roles in the designs of processors,Palabras claves:D3L, dynamic, full-Adder, reliability, Sub-thresholdAutores:Corsonello P., Marco Lanuzza, Margala M., Purohit S.Fuentes:scopusLow-power level shifter for multi-supply voltage designs
ArticleAbstract: In this brief, a new low-power level shifter (LS) is presented for robust logic voltage shifting froPalabras claves:Level shifter (LS), multi-supply voltage design, sub-threshold operation, Ultra-low powerAutores:Corsonello P., Marco Lanuzza, Perri S.Fuentes:scopusImpact of process variations on flip-flops energy and timing characteristics
Conference ObjectAbstract: In this paper, the influence of random process variations on speed and energy consumption of variousPalabras claves:Autores:Corsonello P., Frustaci F., Marco Lanuzza, Perri S., Rose R.D.Fuentes:scopusSelf-repairing SRAM architecture to mitigate the inter-die process variations at 65nm technology
Conference ObjectAbstract: With aggressive scaling, one of the major barriers that CMOS technology faces is the increasing procPalabras claves:Adaptive body biasing, Process variation mitigation technique, Random process variations, SRAM cellAutores:Corsonello P., Kansal S., Marco LanuzzaFuentes:scopus