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IEEE Transactions on Very Large Scale Integration (VLSI) Systems(2)
International Journal of Circuit Theory and Applications(2)
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)(2)
ACM Transactions on Reconfigurable Technology and Systems(1)
IEEE International Symposium on Industrial Electronics(1)
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Ciencias de la computación(7)
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scopus(19)
Comparative analysis of yield optimized pulsed flip-flops
ArticleAbstract: In this paper, the influence of random process variations on pulsed flip-flops is analyzed. Monte CaPalabras claves:Autores:Corsonello P., Frustaci F., Marco Lanuzza, Perri S., Rose R.D.Fuentes:scopusAn efficient and low-cost design methodology to improve SRAM-Based FPGA robustness in space and avionics applications
Conference ObjectAbstract: This paper presents an efficient approach to protect an FPGA design against Single Event Upsets (SEUPalabras claves:Avionics, Fpga, Reconfigurable System, Single Event Upsets, spaceAutores:Corsonello P., Frustaci F., Marco Lanuzza, Perri S., Zicari P.Fuentes:scopusAn efficient wavelet image encoder for FPGA-based designs
Conference ObjectAbstract: This paper presents the design of a new wavelet-based encoder suitable for fast and low-power imagePalabras claves:Autores:Cocorullo G., Corsonello P., Marco Lanuzza, Perri S.Fuentes:scopusA new low-power high-speed single-clock-cycle binary comparator
Conference ObjectAbstract: This paper presents a new ultra-low power high-speed single-clock-cycle binary comparator. It is basPalabras claves:Autores:Corsonello P., Frustaci F., Marco Lanuzza, Perri S.Fuentes:scopusA self-hosting configuration management system to mitigate the impact of radiation-induced multi-bit upsets in SRAM-Based FPGAs
Conference ObjectAbstract: This paper presents an efficient circuit to mitigate the impact of Radiation-Induced Multi-Bit UpsetPalabras claves:Autores:Corsonello P., Frustaci F., Marco Lanuzza, Perri S., Zicari P.Fuentes:scopusDesign and evaluation of an energy-delay-area efficient datapath for coarse-grain reconfigurable computing systems
ArticleAbstract: This paper presents the architecture and complete VLSI implementation of a high data throughput, enePalabras claves:arithmetic circuits, Data path design, Reconfigurable architecturesAutores:Corsonello P., Marco Lanuzza, Margate M., Perri S., Purohit S.Fuentes:scopusDesign and implementation of a 90nm low bit-rate image compression core
Conference ObjectAbstract: This paper presents a low-cost, high throughput Discrete Wavelet Transform-based image compressor. TPalabras claves:Autores:Cocorullo G., Corsonello P., Marco Lanuzza, Perri S., Staino G.Fuentes:scopusDesign of energy aware adder circuits considering random intra-die process variations
ArticleAbstract: Energy consumption is one of the main barriers to current high-performance designs. Moreover, the inPalabras claves:Adder design, Intra-die process variations, Yield-driven designAutores:Corsonello P., Frustaci F., Marco Lanuzza, Perri S.Fuentes:scopusDesign-space exploration of energy-delay-area efficient coarse-grain reconfigurable datapath
Conference ObjectAbstract: This paper presents the VLSI design of a high data throughput, energy and area efficient data path tPalabras claves:Autores:Corsonello P., Marco Lanuzza, Margala M., Perri S., Purohit S.Fuentes:scopusGate-level body biasing technique for high-speed sub-threshold CMOS logic gates
ArticleAbstract: An efficient technique for designing high-performance logic circuits operating in sub-threshold regiPalabras claves:body biasing, Logic gates, sub-threshold CMOS, ultra low-powerAutores:Corsonello P., Marco Lanuzza, Perri S.Fuentes:scopus