Mostrando 8 resultados de: 8
Publisher
IET Computers and Digital Techniques(1)
Journal of Systems Architecture(1)
Journal of Universal Computer Science(1)
Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005(1)
Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL(1)
Área temáticas
Ciencias de la computación(8)
Física aplicada(3)
Métodos informáticos especiales(1)
Programación informática, programas, datos, seguridad(1)
Relaciones internacionales(1)
Área de conocimiento
Arquitectura de computadoras(6)
Ciencias de la computación(4)
Simulación por computadora(4)
Aprendizaje automático(1)
Red informática(1)
Origen
scopus(8)
An approach to execute conditional branches onto SIMD multi-context reconfigurable architectures
Conference ObjectAbstract: Reconfigurable architectures have becoming very relevant in recent years. In this paper we propose aPalabras claves:Autores:Bagherzadeh N., Fernández M., Rivera Calle Fredy, Sânchez-Élez M.Fuentes:scopusConfiguration scheduling for conditional branch execution onto multi-context reconfigurable architectures
Conference ObjectAbstract: This paper addresses the exploitation of the capabilities of multi-context reconfigurable architectuPalabras claves:Autores:Bagherzadeh N., Fernández M., Hermida R., Rivera Calle Fredy, Sânchez-Élez M.Fuentes:scopusDesign and implementation of a rendering algorithm in a SIMD reconfigurable architecture (MorphoSys)
Conference ObjectAbstract: In this paper we analyze a 3D image rendering algorithm and the different mapping schemes to implemePalabras claves:Autores:Bagherzadeh N., Davila J., De Torres A., Rivera Calle Fredy, Sanchez J.M., Sânchez-Élez M.Fuentes:scopusFrom UML specifications to mapping and scheduling of tasks into a NoC, with reliability considerations
ArticleAbstract: This paper describes a technique for performing mapping and scheduling of tasks belonging to an execPalabras claves:Application mapping, Fault tolerance, Multiprocessor system-on-chip (MPSoC), Network-on-chip (NoC), Unified modeling language (UML)Autores:Aedo J.E., Bagherzadeh N., Bolanos F., Rivera Calle FredyFuentes:scopusEfficient mapping of hierarchical trees on coarse-grain reconfigurable architectures
Conference ObjectAbstract: Reconfigurable architectures have become increasingly important in recent years. In this paper we prPalabras claves:computer graphics, Hierarchical trees, Multimedia, Reconfigurable architectures, SIMDAutores:Bagherzadeh N., Fernández M., Hermida R., Rivera Calle Fredy, Sânchez-Élez M.Fuentes:scopusLow power data prefetch for 3D image applications on coarse-grain reconfigurable architectures
Conference ObjectAbstract: In this paper we present a data prefetch policy for the execution of 3D interactive applications onPalabras claves:Autores:Bagherzadeh N., Fernández M., Hermida R., Rivera Calle Fredy, Sânchez-Élez M.Fuentes:scopusMapping and scheduling in heterogeneous NoC through population-based incremental learning
ArticleAbstract: Network-on-Chip (NoC) is a growing and promising communication paradigm for Multiprocessor-System-OnPalabras claves:Computer-aided design (CAD), Multiprocessor-system-on-chip (MPSoC) and network-on-chip (NoC), Population-based incremental learning (PBIL)Autores:Aedo J.E., Bagherzadeh N., Bolanos F., Rivera Calle FredyFuentes:scopusScheduling methodology for conditional execution of kernels onto multicontext reconfigurable architectures
ArticleAbstract: The authors present a scheduling methodology for conditional execution of kernels onto single instruPalabras claves:Autores:Bagherzadeh N., Hermida R., Rivera Calle Fredy, Sânchez-Élez M.Fuentes:scopus