Mostrando 10 resultados de: 12
Filtros aplicados
Publisher
Proceedings - IEEE International Symposium on Circuits and Systems(6)
IEEE Journal of Solid-State Circuits(2)
2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015(1)
2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017(1)
IEEE Solid-State Circuits Letters(1)
Área temáticas
Física aplicada(9)
Ciencias de la computación(3)
Ingeniería y operaciones afines(1)
Programación informática, programas, datos, seguridad(1)
Origen
scopus(12)
A 0.8-V, 1.54-pJ/940-MHz Dual-Mode Logic-Based 16×16-b Booth Multiplier in 16-nm FinFET
ArticleAbstract: The dual-mode logic (DML) defines runtime adapted digital architectures that switch to either improvPalabras claves:Adaptive design, digital signal processing (DSP), Dual-mode logic (DML)Autores:Fish A., Marco Lanuzza, Ramiro Taco, Shavit N., Stanger I.Fuentes:scopusA Method for Mitigation of Droop Timing Errors Including a 500 MHz Droop Detector and Dual Mode Logic
ArticleAbstract: A technique to mitigate timing errors induced by power supply droops is featured. We propose an invePalabras claves:Capacitors, Clocks, Detectors, Inverters, Logic gates, Resonant frequency, timingAutores:Fish A., Ramiro Taco, Shavit N., Shifman Y., Shor J., Stanger I.Fuentes:scopusAn 88-fJ/40-MHz [0.4 V]-0.61-pJ/1-GHz [0.9 V] dual-mode logic 8 × 8 bit multiplier accumulator with a self-adjustment mechanism in 28-nm FD-SOI
ArticleAbstract: The unique ability of dual-mode logic (DML) to self-adapt to computational needs by providing high sPalabras claves:Dual-mode logic (DML), high-speed, Low-power, self-adaptive multiply-accumulate (MAC)Autores:Fish A., Levi I., Marco Lanuzza, Ramiro TacoFuentes:scopusExploiting single-well design for energy-efficient ultra-wide voltage range Dual Mode Logic -based digital circuits in 28nm FD-SOI technology
Conference ObjectAbstract: In this paper we evaluate the implementation options of energy-efficient dual mode logic (DML) circuPalabras claves:Adaptive energy-efficient digital design, Dual mode logic, FD-SOIAutores:Fish A., Marco Lanuzza, Ramiro Taco, Shavit N., Stanger I., Yavits L.Fuentes:scopusEnergy-delay tradeoffs of low-voltage dual mode logic in 28nm FD-SOI
Conference ObjectAbstract: In this paper, the Dual Mode Logic (DML) technique is evaluated on a low-voltage 16-bit Carry Skip APalabras claves:carry skip adder, dual mode logic (DML), Low-voltageAutores:Fish A., Levi I., Marco Lanuzza, Ramiro TacoFuentes:scopusEvaluation of Dual Mode Logic in 28nm FD-SOI technology
Conference ObjectAbstract: For the first time, the Dual Mode Logic (DML) technique is evaluated in 28 nm UTBB FD-SOI technologyPalabras claves:dual mode logic (DML), Low PowerAutores:Fish A., Levi I., Marco Lanuzza, Ramiro TacoFuentes:scopusDual mode logic address decoder
Conference ObjectAbstract: Address decoders are integral components of random access memories. In higher-performance computing,Palabras claves:dual mode logic (DML), Memory address decoderAutores:Fish A., Ramiro Taco, Shavit N., Stanger I., Yavits L.Fuentes:scopusLow voltage logic circuits exploiting gate level dynamic body biasing in 28 nm UTBB FD-SOI
ArticleAbstract: In this paper, the recently proposed gate level body bias (GLBB) technique is evaluated for low voltPalabras claves:Dynamic body biasing, Low-voltage logic design, UTBB FD-SOIAutores:Fish A., Levi I., Marco Lanuzza, Ramiro TacoFuentes:scopusLow voltage ripple carry adder with low-granularity dynamic forward back-biasing in 28 nm UTBB FD-SOI
Conference ObjectAbstract: In this paper, a low voltage ripple-carry adder (RCA), designed for the ultra-thin body and box (UTBPalabras claves:FD-SOI, gate-level body biasing, Single WellAutores:Fish A., Levi I., Marco Lanuzza, Ramiro TacoFuentes:scopusLive Demo: Silicon evaluation of multimode dual mode logic for PVT-aware datapaths
Conference ObjectAbstract: This demo demonstrates the unique capabilities of the multimode Dual Mode Logic (DML) design techniqPalabras claves:Autores:Fish A., Marco Lanuzza, Ramiro Taco, Shavit N., Stanger I.Fuentes:scopus