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Compact Modeling of Perpendicular STT-MTJs with Double Reference Layers
ArticleAbstract: This paper shows the steps to set up a simulation framework for perpendicular spin-transfer torque (Palabras claves:compact model, Double-barrier MTJ, non-volatile flip-flop (NVFF), STT switchingAutores:Carpentieri M., Crupi F., D'Aquino M., Finocchio G., Marco Lanuzza, Rose R.D.Fuentes:scopusComparative analysis of yield optimized pulsed flip-flops
ArticleAbstract: In this paper, the influence of random process variations on pulsed flip-flops is analyzed. Monte CaPalabras claves:Autores:Corsonello P., Frustaci F., Marco Lanuzza, Perri S., Rose R.D.Fuentes:scopusAssessment of 2D-FET Based Digital and Analog Circuits on Paper
ArticleAbstract: Two-dimensional (2D) materials represent an emerging technology for transistor electronics in view oPalabras claves:2d materials, Field-Effect Transistor (FET), Molybdenum disulfide (MoS ) 2, Paper electronics, Verilog-A modelAutores:Crupi F., Iannaccone G., Marco Lanuzza, Rose R.D., Vatalaro M.Fuentes:scopusAssessment of InAs/AlGaSb Tunnel-FET Virtual Technology Platform for Low-Power Digital Circuits
ArticleAbstract: In this work, a complementary InAs/Al0.05Ga0.95Sb tunnel field-effect-Transistor (TFET) virtual techPalabras claves:full-Adder, III-V, tunnel field effect transistor (TFET), very large scale integration (VLSI).Autores:Crupi F., Esseni D., Marco Lanuzza, Palestri P., Selmi L., Strangio S.Fuentes:scopusAssessment of STT-MRAM performance at nanoscaled technology nodes using a device-to-memory simulation framework
ArticleAbstract: This paper deals with the technology scalability of spin-transfer torque magnetic RAMs (STT-MRAMs)baPalabras claves:Device-to-memory analysis, FinFET, Magnetic tunnel junction (MTJ), STT-MRAM, technology scalingAutores:Crupi F., Esteban Garzón, Marco Lanuzza, Rose R.D., Trojman L.Fuentes:scopusAssessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework
ArticleAbstract: This paper explores non-volatile cache memories implemented by spin-transfer torque magnetic randomPalabras claves:cache memory, Device-to-system simulation framework, double-barrier magnetic tunnel junction (DMTJ), FinFET, STT-MRAMAutores:Carpentieri M., Crupi F., Esteban Garzón, Finocchio G., Marco Lanuzza, Rose R.D., Trojman L.Fuentes:scopusAssessment of paper-based MoS<inf>2</inf> FET for Physically Unclonable Functions
ArticleAbstract: Two-dimensional (2D) materials are recognized as a promising beyond-CMOS technology thanks to theirPalabras claves:2d materials, Hardware security, Molybdenum disulfide (MoS ) 2, Paper electronics, physically unclonable function (PUF), Verilog-A modelAutores:Conti S., Crupi F., Iannaccone G., Magnone P., Marco Lanuzza, Rose R.D., Vatalaro M.Fuentes:scopusBenchmarks of a III-V TFET technology platform against the 10-nm CMOS FinFET technology node considering basic arithmetic circuits
ArticleAbstract: In this work, a benchmark for low-power digital applications of a III-V TFET technology platform agaPalabras claves:Full adders, III-V, Ripple carry adders, TFETAutores:Crupi F., Esseni D., Marco Lanuzza, Palestri P., Selmi L., Strangio S.Fuentes:scopusAn efficient and low-cost design methodology to improve SRAM-Based FPGA robustness in space and avionics applications
Conference ObjectAbstract: This paper presents an efficient approach to protect an FPGA design against Single Event Upsets (SEUPalabras claves:Avionics, Fpga, Reconfigurable System, Single Event Upsets, spaceAutores:Corsonello P., Frustaci F., Marco Lanuzza, Perri S., Zicari P.Fuentes:scopusAn efficient wavelet image encoder for FPGA-based designs
Conference ObjectAbstract: This paper presents the design of a new wavelet-based encoder suitable for fast and low-power imagePalabras claves:Autores:Cocorullo G., Corsonello P., Marco Lanuzza, Perri S.Fuentes:scopus