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Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)(2)
2009 IEEE International Workshop on Medical Measurements and Applications, MeMeA 2009(1)
IEEE Transactions on Circuits and Systems II: Express Briefs(1)
IET Circuits, Devices and Systems(1)
Journal of Low Power Electronics(1)
Área temáticas
Física aplicada(6)
Ciencias de la computación(5)
Programación informática, programas, datos, seguridad(2)
Ingeniería y operaciones afines(1)
Medicina y salud(1)
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Ciencias de la computación(5)
Arquitectura de computadoras(4)
Ingeniería electrónica(2)
Simulación por computadora(2)
Procesamiento de señales(1)
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scopus(8)
An efficient and low-cost design methodology to improve SRAM-Based FPGA robustness in space and avionics applications
Conference ObjectAbstract: This paper presents an efficient approach to protect an FPGA design against Single Event Upsets (SEUPalabras claves:Avionics, Fpga, Reconfigurable System, Single Event Upsets, spaceAutores:Corsonello P., Frustaci F., Marco Lanuzza, Perri S., Zicari P.Fuentes:scopusA novel ICA-based hardware system for reconfigurable and portable BCI
Conference ObjectAbstract: Partially or completely paralyzed patients can benefit from Brain Computer Interface (BCI) in whichPalabras claves:Autores:Calabrese B., Cocorullo G., Gambardella A., Marco Lanuzza, Palumbo A., Sturniolo M., Veltri P., Vizza P.Fuentes:scopusDesign and evaluation of an energy-delay-area efficient datapath for coarse-grain reconfigurable computing systems
ArticleAbstract: This paper presents the architecture and complete VLSI implementation of a high data throughput, enePalabras claves:arithmetic circuits, Data path design, Reconfigurable architecturesAutores:Corsonello P., Marco Lanuzza, Margate M., Perri S., Purohit S.Fuentes:scopusDesign-space exploration of energy-delay-area efficient coarse-grain reconfigurable datapath
Conference ObjectAbstract: This paper presents the VLSI design of a high data throughput, energy and area efficient data path tPalabras claves:Autores:Corsonello P., Marco Lanuzza, Margala M., Perri S., Purohit S.Fuentes:scopusDesigning high-speed adders in power-constrained environments
ArticleAbstract: Data-driven dynamic logic (D3L) is very efficient when low-power constraints are mandatory. UnfortunPalabras claves:Clock-precharged dynamic logic, Data-driven dynamic logic (D3L), Data-precharged dynamic logic, Parallel prefix adderAutores:Corsonello P., Frustaci F., Marco Lanuzza, Perri S., Zicari P.Fuentes:scopusEnergy efficient coarse-grain reconfigurable array for accelerating digital signal processing
Conference ObjectAbstract: In this paper, the architecture of a novel reconfigurable array, optimized for high-throughput and lPalabras claves:Coarse-grain array, DSP, Reconfigurable systemsAutores:Corsonello P., Marco Lanuzza, Margala M., Perri S.Fuentes:scopusNew performance/power/area efficient, reliable full adder design
Conference ObjectAbstract: Arithmetic circuits have always played one of the most important roles in the designs of processors,Palabras claves:D3L, dynamic, full-Adder, reliability, Sub-thresholdAutores:Corsonello P., Marco Lanuzza, Margala M., Purohit S.Fuentes:scopusLow-power split-path data-driven dynamic logic
ArticleAbstract: Data-pre-charged dynamic logic, also known as data-driven dynamic logic (D3L), is very efficient whePalabras claves:Autores:Corsonello P., Frustaci F., Marco Lanuzza, Perri S., Zicari P.Fuentes:scopus