Energy efficient coarse-grain reconfigurable array for accelerating digital signal processing

Abstract:

In this paper, the architecture of a novel reconfigurable array, optimized for high-throughput and low-power Digital Signal Processing, is described. The proposed reconfigurable system consists of 2D array of homogeneous coarse-grain reconfigurable cells organized into a hierarchical two-level architecture. The system has been characterized for performing different DSP tasks. Comparison results demonstrate speedups up to 8X with energy efficiency improvement up to 58% over a state of the art FPGA. © 2009 Springer Berlin Heidelberg.

Año de publicación:

2009

Keywords:

• Reconfigurable systems
• DSP
• Coarse-grain array

Fuente:

scopus