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Analyzing noise robustness of wide fan-in dynamic logic gates under process variations
ArticleAbstract: Wide fan-in dynamic logic gates are difficult to design due to the large number of leaky evaluationPalabras claves:Dynamic logic, process variations, wide fan-inAutores:Corsonello P., Frustaci F., Marco Lanuzza, Perri S.Fuentes:scopusA physical unclonable function based on a 2-transistor subthreshold voltage divider
ArticleAbstract: In this paper, a compact circuit solution for silicon-based static physical unclonable functions (PUPalabras claves:analog design, CMOS design, Hardware security, physical unclonable functions (PUFs), subthreshold operation, variabilityAutores:Albano D., Crupi F., Marco Lanuzza, Rose R.D.Fuentes:scopusA portable class of 3-transistor current references with low-power sub-0.5 V operation
ArticleAbstract: This work proposes a new class of current references based on only 3 transistors that allows sub-0.5Palabras claves:CMOS analog design, Current reference, internet of things (IoT), Low-power, Low-voltageAutores:Crupi F., Iannaccone G., Marco Lanuzza, Paliy M., Perna M., Rose R.D.Fuentes:scopusDesign of high-speed low-power parallel-prefix adder trees in nanometer technologies
ArticleAbstract: This paper presents a novel approach to design high-speed low-power parallel-prefix adder trees. SubPalabras claves:Brent-Kung adder tree, High-speed addition, Parallel-Prefix addersAutores:Corsonello P., Marco Lanuzza, Perri S.Fuentes:scopusGate-level body biasing for subthreshold logic circuits: Analytical modeling and design guidelines
ArticleAbstract: Gate-level body biasing provides an attractive solution to increase speed and robustness against proPalabras claves:digital circuits, forward body biasing, subthreshold design, Ultra-low voltageAutores:Albano D., Crupi F., Marco Lanuzza, Ramiro TacoFuentes:scopusGate-level body biasing technique for high-speed sub-threshold CMOS logic gates
ArticleAbstract: An efficient technique for designing high-performance logic circuits operating in sub-threshold regiPalabras claves:body biasing, Logic gates, sub-threshold CMOS, ultra low-powerAutores:Corsonello P., Marco Lanuzza, Perri S.Fuentes:scopusEnergy-efficient single-clock-cycle binary comparator
ArticleAbstract: A new fast low-power single-clock-cycle binary comparator is presented. High speed is assured by usiPalabras claves:arithmetic circuits, binary comparator, CMOS, Low-powerAutores:Corsonello P., Frustaci F., Marco Lanuzza, Perri S.Fuentes:scopusLow energy/delay overhead level shifter for wide-range voltage conversion
ArticleAbstract: Multi-supply voltage systems on chip have been widely explored for energy-efficient elaborations. APalabras claves:Level shifter (LS), multi-supply voltage design, subthreshold operation, ultra-low-voltage interfaceAutores:Crupi F., Iannaccone G., Marco Lanuzza, Rao S., Rose R.D.Fuentes:scopus