Mostrando 10 resultados de: 34
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Assessment of STT-MRAM performance at nanoscaled technology nodes using a device-to-memory simulation framework
ArticleAbstract: This paper deals with the technology scalability of spin-transfer torque magnetic RAMs (STT-MRAMs)baPalabras claves:Device-to-memory analysis, FinFET, Magnetic tunnel junction (MTJ), STT-MRAM, technology scalingAutores:Crupi F., Esteban Garzón, Marco Lanuzza, Rose R.D., Trojman L.Fuentes:scopusAssessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework
ArticleAbstract: This paper explores non-volatile cache memories implemented by spin-transfer torque magnetic randomPalabras claves:cache memory, Device-to-system simulation framework, double-barrier magnetic tunnel junction (DMTJ), FinFET, STT-MRAMAutores:Carpentieri M., Crupi F., Esteban Garzón, Finocchio G., Marco Lanuzza, Rose R.D., Trojman L.Fuentes:scopusAM<sup>4</sup>: MRAM Crossbar Based CAM/TCAM/ACAM/AP for In-Memory Computing
ArticleAbstract: In-memory computing seeks to minimize data movement and alleviate the memory wall by computing in-siPalabras claves:associative memories, associative processor, CAM, Double-barrier MTJ, emerging memories, MRAM, MTJ, Non-von Neumann computer architecture, TCAMAutores:Esteban Garzón, Marco Lanuzza, Teman A., Yavits L.Fuentes:scopusA 0.05 mm², 350 mV, 14 nW Fully-Integrated Temperature Sensor in 180-nm CMOS
ArticleAbstract: In this brief, we present a fully-integrated ring-oscillator based CMOS temperature sensor for InterPalabras claves:CMOS-based temperature sensor, Low-power, Low-voltage, Real-time sensing, Ring oscillatorAutores:Benjamin Zambrano, Crupi F., Esteban Garzón, Marco Lanuzza, Strangio S.Fuentes:scopusA 0.6V-1.8V Compact Temperature Sensor with 0.24 °c Resolution, ±1.4 °c Inaccuracy and 1.06nJ per Conversion
ArticleAbstract: This paper presents a fully-integrated CMOS temperature sensor for densely-distributed thermal monitPalabras claves:CMOS temperature sensor, Dynamic voltage and frequency scaling, Sub-threshold, Thermal monitoringAutores:Benjamin Zambrano, Esteban Garzón, Iannaccone G., Marco Lanuzza, Strangio S.Fuentes:scopusA Low-Energy DMTJ-Based Ternary Content- Addressable Memory With Reliable Sub-Nanosecond Search Operation
ArticleAbstract: In this paper, we propose an energy-efficient, reliable, hybrid, 10-transistor/2-Double-Barrier-MagnPalabras claves:Double-barrier MTJ, energy-efficiency, Low-power, non-volatile TCAM (NV-TCAM)Autores:Carpentieri M., Esteban Garzón, Finocchio G., Marco Lanuzza, Teman A., Yavits L.Fuentes:scopusA RISC-V-based Research Platform for Rapid Design Cycle
Conference ObjectAbstract: This work proposes a novel platform for bringing a project from the concept to the tapeout stage inPalabras claves:Autores:Esteban Garzón, Golman R., Harel O., Kra Y., Marco Lanuzza, Noy T., Pollock A., Rudin Y., Shoshan Y., Teman A., Weitzman Y., Yuzhaninov S.Fuentes:scopusAIDA: Associative In-Memory Deep Learning Accelerator
ArticleAbstract: This work presents an associative in-memory deep learning processor (AIDA) for edge devices. An assoPalabras claves:Autores:Esteban Garzón, Marco Lanuzza, Teman A., Yavits L.Fuentes:scopusDevice-to-system level simulation framework for STT-DMTJ based cache memory
Conference ObjectAbstract: This paper presents a comparative study on non-volatile cache memories based on nanoscaled spin-tranPalabras claves:Device-to-system simulation framework, Double-barrier magnetic tunnel junction, STT-MRAMAutores:Crupi F., Esteban Garzón, Marco Lanuzza, Rose R.D.Fuentes:scopusCapacitance Extraction of 34-nm Metallurgical Channel Length MOSFET for Parasitic Assessment Using the RFCV Technique
Conference ObjectAbstract: This paper presents the description and the results obtained with a new RFCV system written on pythoPalabras claves:Parameter Analyzer, PYTHON, RFCV, Source Measure Unit, Vector Network AnalyzerAutores:DIego R. Benalcázar, Esteban Garzón, Trojman L.Fuentes:scopus