Mostrando 10 resultados de: 21
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2019 IEEE 4th Ecuador Technical Chapters Meeting, ETCM 2019(2)
2020 IEEE ANDESCON, ANDESCON 2020(2)
2022 IEEE 13th Latin American Symposium on Circuits and Systems, LASCAS 2022(2)
Electronics (Switzerland)(2)
Solid-State Electronics(2)
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Ingeniería electrónica(12)
Ciencias de la computación(7)
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Ciencia de materiales(3)
720p-HD Gray-scale and Color Images Shape Recognition System Implementation on an FPGA Platform with a 1080pFull-HD HDMI Interface using a Hu Moments Algorithm
Conference ObjectAbstract: The present work implements and adapts a fast shape recognition algorithm on the Xilinx VC707 VIRTEXPalabras claves:ADV7511, Fpga, Full-HD, Gray Scale, HDL, HDMI, IIC, RGB, Shape recognitionAutores:André Borja, Daniel Cárdenas, Felipe Toscano, Luis Miguel Procel Moya, Ramiro Taco, Trojman L.Fuentes:scopusA low-voltage, low-power reconfigurable current-mode softmax circuit for analog neural networks
ArticleAbstract: This paper presents a novel low-power low-voltage analog implementation of the softmax function, witPalabras claves:Activation functions, Deep Neural Networks, Machine learning, SoftmaxAutores:Crupi F., Marco Lanuzza, Strangio S., Tatiana Moposita, Trojman L., Vatalaro M., Vladimirescu A.Fuentes:scopusAssessment of STT-MRAM performance at nanoscaled technology nodes using a device-to-memory simulation framework
ArticleAbstract: This paper deals with the technology scalability of spin-transfer torque magnetic RAMs (STT-MRAMs)baPalabras claves:Device-to-memory analysis, FinFET, Magnetic tunnel junction (MTJ), STT-MRAM, technology scalingAutores:Crupi F., Esteban Garzón, Marco Lanuzza, Rose R.D., Trojman L.Fuentes:scopusAssessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework
ArticleAbstract: This paper explores non-volatile cache memories implemented by spin-transfer torque magnetic randomPalabras claves:cache memory, Device-to-system simulation framework, double-barrier magnetic tunnel junction (DMTJ), FinFET, STT-MRAMAutores:Carpentieri M., Crupi F., Esteban Garzón, Finocchio G., Marco Lanuzza, Rose R.D., Trojman L.Fuentes:scopusDMTJ-Based Non-Volatile Ternary Content Addressable Memory for Energy-Efficient High-Performance Systems
Conference ObjectAbstract: This paper explores performance of non-volatile ternary content addressable memories (NV-TCAMs), expPalabras claves:Double-barrier magnetic tunnel junction, energy-efficiency, Ternary content-addressable memoriesAutores:Kevin Vicuña, Luis Miguel Procel Moya, Ramiro Taco, Trojman L.Fuentes:googlescopusEffects of the technology scaling down to 28nm on Ultra-Low Voltage and Power OTA performance using TCAD simulations
Conference ObjectAbstract: In this paper, the effect on the performances of the technology scaling down to 28nm (bulk and planaPalabras claves:28nm, 90nm, Feed Forward rejection, OTA, PDK, Pseudo Differential Pair, TCAD simulation, Ultra-low power, Ultra-low voltageAutores:André Borja, Juan Orozco, Luis Miguel Procel Moya, Mateo Bonilla, Mateo Valencia, Ramiro Taco, Trojman L.Fuentes:scopusEfficiency of Double-Barrier Magnetic Tunnel Junction-Based Digital eNVM Array for Neuro-Inspired Computing
ArticleAbstract: This brief deals with the impact of spin-transfer torque magnetic random access memory (STT-MRAM) cePalabras claves:double-barrier magnetic tunnel junction (DMTJ), energy-efficiency, MNIST dataset, multilayer perceptron (MPL), online classification, STT-MRAMAutores:Crupi F., Esteban Garzón, Marco Lanuzza, Tatiana Moposita, Trojman L., Vladimirescu A.Fuentes:scopusHigh-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator
Conference ObjectAbstract: This paper presents an energy-efficient single-clock-cycle binary Dual-Mode Logic (DML)-based comparPalabras claves:arithmetic circuits, binary comparator, CMOS, Dual-mode logicAutores:Luis Miguel Procel Moya, Marco Lanuzza, Ramiro Taco, Ricardo Escobar, Trojman L.Fuentes:scopusImplementation and Comparison of a Fast Shape Recognition Algorithm using Different FPGA Platforms
Conference ObjectAbstract: In the present work, we implement and compare a fast shape recognition algorithm in two FPGA platforPalabras claves:computer vison, Fpga, HDL, Shape recognitionAutores:André Borja, Daniel Cárdenas, Germán Arévalo Bermeo, Luis Miguel Procel Moya, Trojman L., Varengues G.Fuentes:scopusImplementation of 32nm MD5 Crypto-Processor using Different Topographical Synthesis Techniques and Comparison with 500nm Node
Conference ObjectAbstract: This work focuses on several synthetizations developed in both 32nm and 500nm technologies to evaluaPalabras claves:32nm Technology, Integrated circuit, MD5, Synopsys, Synthesis Guide, technology scaling, Topographical SynthesisAutores:André Borja, Juan José Jiménez, Luis Miguel Procel Moya, Ramiro Taco, Silly L., Trojman L.Fuentes:scopus