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Compact Modeling of Perpendicular STT-MTJs with Double Reference Layers
ArticleAbstract: This paper shows the steps to set up a simulation framework for perpendicular spin-transfer torque (Palabras claves:compact model, Double-barrier MTJ, non-volatile flip-flop (NVFF), STT switchingAutores:Carpentieri M., Crupi F., D'Aquino M., Finocchio G., Marco Lanuzza, Rose R.D.Fuentes:scopusComparative analysis of yield optimized pulsed flip-flops
ArticleAbstract: In this paper, the influence of random process variations on pulsed flip-flops is analyzed. Monte CaPalabras claves:Autores:Corsonello P., Frustaci F., Marco Lanuzza, Perri S., Rose R.D.Fuentes:scopusAssessment of 2D-FET Based Digital and Analog Circuits on Paper
ArticleAbstract: Two-dimensional (2D) materials represent an emerging technology for transistor electronics in view oPalabras claves:2d materials, Field-Effect Transistor (FET), Molybdenum disulfide (MoS ) 2, Paper electronics, Verilog-A modelAutores:Crupi F., Iannaccone G., Marco Lanuzza, Rose R.D., Vatalaro M.Fuentes:scopusAssessment of STT-MRAM performance at nanoscaled technology nodes using a device-to-memory simulation framework
ArticleAbstract: This paper deals with the technology scalability of spin-transfer torque magnetic RAMs (STT-MRAMs)baPalabras claves:Device-to-memory analysis, FinFET, Magnetic tunnel junction (MTJ), STT-MRAM, technology scalingAutores:Crupi F., Esteban Garzón, Marco Lanuzza, Rose R.D., Trojman L.Fuentes:scopusAssessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework
ArticleAbstract: This paper explores non-volatile cache memories implemented by spin-transfer torque magnetic randomPalabras claves:cache memory, Device-to-system simulation framework, double-barrier magnetic tunnel junction (DMTJ), FinFET, STT-MRAMAutores:Carpentieri M., Crupi F., Esteban Garzón, Finocchio G., Marco Lanuzza, Rose R.D., Trojman L.Fuentes:scopusAssessment of paper-based MoS<inf>2</inf> FET for Physically Unclonable Functions
ArticleAbstract: Two-dimensional (2D) materials are recognized as a promising beyond-CMOS technology thanks to theirPalabras claves:2d materials, Hardware security, Molybdenum disulfide (MoS ) 2, Paper electronics, physically unclonable function (PUF), Verilog-A modelAutores:Conti S., Crupi F., Iannaccone G., Magnone P., Marco Lanuzza, Rose R.D., Vatalaro M.Fuentes:scopusAn energy aware variation-tolerant writing termination control for STT-based non volatile flip-flops
Conference ObjectAbstract: In this paper, we propose a variation-tolerant design methodology to embed self-write termination coPalabras claves:digital circuits, Energy efficiency, Non-volatile flip-flop, STT-MRAM, VLSI, Zero-leakage circuitsAutores:Alioto M., Crupi F., Marco Lanuzza, Rose R.D.Fuentes:scopusA 0.25-V, 5.3-pW Voltage Reference with 25-μV/°C Temperature Coefficient, 140-μV/V Line Sensitivity and 2,200-μm<sup>2</sup> Area in 180nm
Conference ObjectAbstract: This work introduces a compact voltage reference operating at pW-power and 250-mV supply (e.g., direPalabras claves:Autores:Alioto M., Crupi F., Fassio L., Lin L., Marco Lanuzza, Rose R.D.Fuentes:scopusA 0.6-to-1.8V CMOS Current Reference with Near-100% Power Utilization
ArticleAbstract: In this brief, a current reference is proposed to introduce the new capability of operating under wiPalabras claves:area-efficient, Current reference, internet of things, Low Power, Low voltage, Sensor nodesAutores:Alioto M., Crupi F., Fassio L., Lin L., Marco Lanuzza, Rose R.D.Fuentes:scopusA 3.2-pW, 0.2-V Trimming-Less Voltage Reference with 1.4-mV Across-Wafer Total Accuracy
Conference ObjectAbstract: This work introduces a class of voltage references able to operate down to 3.2 pW and 0.2-V supply fPalabras claves:corner-aware, energy harvesting, Ultra-low voltage, Voltage referenceAutores:Alioto M., Crupi F., Fassio L., Lin L., Marco Lanuzza, Rose R.D.Fuentes:scopus