Assessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework

Article

Abstract: This paper explores non-volatile cache memories implemented by spin-transfer torque magnetic random

Palabras claves:

cache memory, Device-to-system simulation framework, double-barrier magnetic tunnel junction (DMTJ), FinFET, STT-MRAM

Autores:

Carpentieri M., Crupi F., Esteban Garzón, Finocchio G., Marco Lanuzza, Rose R.D., Trojman L.

Fuentes:

scopus