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SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings(1)
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Assessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework
ArticleAbstract: This paper explores non-volatile cache memories implemented by spin-transfer torque magnetic randomPalabras claves:cache memory, Device-to-system simulation framework, double-barrier magnetic tunnel junction (DMTJ), FinFET, STT-MRAMAutores:Carpentieri M., Crupi F., Esteban Garzón, Finocchio G., Marco Lanuzza, Rose R.D., Trojman L.Fuentes:scopusExploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs
Conference ObjectAbstract: This paper explores performance and technology-scalability of STT-MRAMs exploiting double-barrier MTPalabras claves:double-barrier magnetic tunnel junction (DMTJ), FinFET, STT-MRAM, technology-voltage scalingAutores:Carpentieri M., Crupi F., Esteban Garzón, Finocchio G., Marco Lanuzza, Rose R.D., Trojman L.Fuentes:scopus