Hybrid clock recovery for a gigabit POF transceiver implemented on FPGA

Article

Abstract: In this paper, we present a clock recovery system implemented on field programmable gate array and i

Palabras claves:

Clock recovery (CR), DSP, Field programmable gate array (FPGA), Gigabit Ethernet, Optical Communications, phase-locked loop (PLL), Polymer Optical Fiber, timing error detector (TED)

Autores:

Abrate S., Nespola A., Ramirez J., Roberto Gaudino, Savio P., Straullu S.

Fuentes:

scopus