Mostrando 7 resultados de: 7
Filtros aplicados
Publisher
Proceedings - IEEE International Symposium on Circuits and Systems(4)
2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018(1)
IEEE Journal of Solid-State Circuits(1)
IEEE Solid-State Circuits Letters(1)
Área temáticas
Ciencias de la computación(3)
Economía(1)
Ingeniería y operaciones afines(1)
Programación informática, programas, datos, seguridad(1)
Ética del trabajo(1)
Área de conocimiento
Ingeniería electrónica(5)
Arquitectura de computadoras(2)
Algoritmo(1)
Fotovoltaica(1)
Origen
scopus(7)
A Method for Mitigation of Droop Timing Errors Including a 500 MHz Droop Detector and Dual Mode Logic
ArticleAbstract: A technique to mitigate timing errors induced by power supply droops is featured. We propose an invePalabras claves:Capacitors, Clocks, Detectors, Inverters, Logic gates, Resonant frequency, timingAutores:Fish A., Ramiro Taco, Shavit N., Shifman Y., Shor J., Stanger I.Fuentes:scopusExploiting single-well design for energy-efficient ultra-wide voltage range Dual Mode Logic -based digital circuits in 28nm FD-SOI technology
Conference ObjectAbstract: In this paper we evaluate the implementation options of energy-efficient dual mode logic (DML) circuPalabras claves:Adaptive energy-efficient digital design, Dual mode logic, FD-SOIAutores:Fish A., Marco Lanuzza, Ramiro Taco, Shavit N., Stanger I., Yavits L.Fuentes:scopusFlexDML: High Utilization Configurable Multimode Arithmetic Units Featuring Dual Mode Logic
ArticleAbstract: Dual mode logic (DML) enables flexible energy-delay (ED) optimization. By setting the design elementPalabras claves:Arithmetic, CMOS, configurable computing, DML, dual mode logic (DML), dynamic, mixed-mode, Pipeline, staticAutores:Fish A., Levi I., Marco Lanuzza, Ramiro Taco, Shavit N., Stanger I., Yavits L.Fuentes:scopusDual mode logic address decoder
Conference ObjectAbstract: Address decoders are integral components of random access memories. In higher-performance computing,Palabras claves:dual mode logic (DML), Memory address decoderAutores:Fish A., Ramiro Taco, Shavit N., Stanger I., Yavits L.Fuentes:scopusLive Demo: Silicon evaluation of multimode dual mode logic for PVT-aware datapaths
Conference ObjectAbstract: This demo demonstrates the unique capabilities of the multimode Dual Mode Logic (DML) design techniqPalabras claves:Autores:Fish A., Marco Lanuzza, Ramiro Taco, Shavit N., Stanger I.Fuentes:scopusLive demonstration: A 0.8V, 1.54 pJ / 940 MHz dual mode logic-based 16x16-bit booth multiplier in 16-nm FinFET
Conference ObjectAbstract: The Dual Mode Logic (DML) defines run-time adaptive digital architectures that switch to either imprPalabras claves:Autores:Fish A., Marco Lanuzza, Ramiro Taco, Shavit N., Stanger I.Fuentes:scopusProcess variation-aware datapath employing dual mode logic
Conference ObjectAbstract: Dual Mode Logic (DML), which was recently introduced by our group, offers the possibility to operatePalabras claves:dual mode logic (DML), Dynamic logic, Process variation, Static cmos, Ultra-low voltageAutores:Fish A., Ramiro Taco, Shavit N., Stanger I.Fuentes:scopus